gem5-accel: A Pre-RTL Simulation Toolchain for Accelerator Architecture Validation
Vieira, J.
; Roma, N
;
Falcão, G.
; Tomás, P.
IEEE Computer Architecture Letters Vol. 23, Nº 1, pp. 1 - 4, January, 2024.
ISSN (print): 1556-6056
ISSN (online): 1556-6064
Scimago Journal Ranking: 0,83 (in 2023)
Digital Object Identifier: 10.1109/LCA.2023.3329443
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Abstract
Attaining the performance and efficiency levels required by modern applications often requires the use of application-specific accelerators. However, writing synthesizable Register-Transfer Level code for such accelerators is a complex, expensive, and time-consuming process, which is cumbersome for early architecture development phases. To tackle this issue, a pre-synthesis simulation toolchain is herein proposed that facilitates the early architectural evaluation of complex accelerators aggregated to multi-level memory hierarchies. To demonstrate its usefulness, the proposed gem5-accel is used to model a tensor accelerator based on Gemmini, showing that it can successfully anticipate the results of complex hardware accelerators executing deep Neural Network models.
