Date: December, 11 2017 2:30pm – 4:30pm
Place: ISCTE-IUL Room: Auditorio J.J. Laginha
The need for ever more powerful supercomputers does not appear to be slowing down, but the challenges to push computing to exaFLOP levels and beyond are becoming increasingly difficult. Targets for computing throughput, memory capacity, memory bandwidth, power efficiency, reliability, and cost make the construction of an Exascale machine to be a significant challenge. In this talk, I will first present an overview of current AMD technologies, and then I will describe one possible vision for a processor architecture that can be used to construct Exascale systems. We describe a conceptual Exascale Node Architecture (ENA), which is a computational building block for an Exascale supercomputer. The ENA consists of an Exascale Heterogeneous Processor (EHP) coupled with an advanced memory system. The conceptual EHP provides a high-performance accelerated processing unit (CPU+GPU), in-package high-bandwidth 3D memory, and aggressive use of die-stacking and chiplet technologies to meet the requirements for Exascale computing in a balanced manner. In addition to detailing our approach, I will also discuss some of the remaining open research challenges for the community. More Information..
ISWCS 2018, Lisbon, Portugal, 28-31 August
Technically Co-Sponsored by IEEE ComSoc, IEEE VTS and EURASIP
Paper Submission Deadline: April 06, 2018
ISWCS’2018 will be held in Lisbon city center (at the ISCTE-IUL campus), a historical city full of stories to tell, where the sun shines 290 days a year and you feel safe wandering around day or night. Lisbon is full of authenticity where old customs and ancient history intermix with cultural entertainment and hi-tech innovation. It’s a city famous for its hospitality and the family-like way it welcomes visitors. More Information..