Creating and sharing knowledge for telecommunications

A Novel Macroblock-Level Filtering Upsampling Architecture for H.264/AVC Scalable Extension

Silva, T. ; Cruz, L. A. S. C. ; Agostini, L.

Journal of Integrated Circuits and Systems Vol. 6, Nº 1, pp. 43 - 49, March, 2011.

ISSN (print): 1807-1953
ISSN (online): 1872-0234

Journal Impact Factor: (in 0)

Digital Object Identifier:

The scalable extension of the H.264/AVC standard, also called H.264/AVC SVC standard or simply SVC standard uses spatial upsampling in the spatial scalability modes. This work presents a novel upsampling architecture designed for operation at macroblock level and dyadic upsampling ratio with QVGA as the base layer resolution and VGA as the en-hancement resolution. The adoption of a macroblock-level solution translates into a more efficient use of hardware resources with savings of approximately 25% in the number of ALUTs and DLRs and using about two hundred times less memory bits, when compared to previously published works. The designed architecture was synthesized targeting four FPGAs: Altera Cyclone III and Stratix IV and Xilinx Spartan 3E and Virtex 4. The best throughput was reached by the Xilinx Virtex 4 device, with a processing rate of 506 VGA frames per second. The worst result was reached by the Xilinx Spartan 3E FPGA, with 249 VGA frames per second. All target FPGAs surpasses the necessary throughput to decode VGA videos in real time. This very high throughput is important especially when low power applications are considered, since with low operation frequencies (9.34MHz) it is possible to reach real time (30 frames per second) for all target FPGAs.