A Dynamic Jitter Model to Evaluate Uncertainty Trends with Technology Scaling
Integration, The VLSI Journal Vol. 45, Nº 2, pp. 162 - 171, March, 2012.
ISSN (print): 0167-9260
ISSN (online): 0167-9260
Journal Impact Factor: 0,703 (in 2015)
Digital Object Identifier: 10.1016/j.vlsi.2011.11.002
Clock jitter can no longer be considered negligible when compared to clock skew. Its unpredictability and high-frequency content makes it an increasingly limiting factor to performance in modern digital systems. In this paper, we investigate dynamic jitter and uncertainty trends, as technology continues scaling to the nanometric region. Simulation results are used to derive heuristic metrics for the sensitivity of a generic repeater to dynamic variability sources. These metrics are then used to discuss clock precision degradation with technology scaling. Using parameters that can be easily obtained, the proposed model can be useful to assess the expected behavior of existing and future technologies in terms of clock precision. Also, it provides a valuable insight regarding the key circuit parameters responsible for dynamic jitter insertion.