The ARPA-MT Embedded SMT Processor and Its RTOS Hardware Accelerator
; Ferrari, ABF
IEEE Transactions on Industrial Electronics Vol. 58, Nº 3, pp. 890 - 904, March, 2011.
ISSN (print): 0278-0046
ISSN (online): 0278-0046
Scimago Journal Ranking: 1,95 (in 2011)
Digital Object Identifier: 10.1109/TIE.2009.2028359
The high-level modelling and parametrization capabilities of current hardware description languages, as well as the huge integration capacity and flexibility provided by modern FPGAs, opens the way to designing processors tuned to given applications and favoring specific properties. This paper presents the ARPA-MT processor - a customizable, synthesizable and time predictable processor model optimized for multitasking real-time embedded systems, which efficiently explores modern FPGA technology. A fundamental processor component is the ARPA-OSC coprocessor designed for hardware implementation of the basic real-time operating system management functions, such as timing, task scheduling, synchronization and switching, efficient interrupt handling and verification of the timing constraints. The hardware implementation of these functions allows executing them faster and more predictably, reducing the operating system overhead and improving its determinism. The performance evaluation has shown reductions of one to two orders of magnitude in the execution time of some functions of a real-time executive, in comparison with an analogous software implementation.