Automatic Topology Selection and Sizing of Class-D Loop-Filters for Minimizing Distortion Based on an Evolutionary Optimization Kernel
Guilherme, DG
;
Guilherme, J.G.
;
Horta, N.
Analog Integrated Circuits and Signal Processing Vol. 73, Nº 10.1007/s10470-011-9716-4, pp. 21 - 32, October, 2012.
ISSN (print): 0925-1030
ISSN (online): 1573-1979
Scimago Journal Ranking: 0,25 (in 2012)
Digital Object Identifier: 10.1007/s10470-011-9716-4
Abstract
This paper presents an optimization methodology for continuous time loop-filters design applied to Class-D amplifiers. The methodology is based on an evolutionary optimization approach which integrates both the topology selection and circuit sizing by automatically generating optimal sized topologies and performance tradeoffs for the Class-D amplifier. The presented approach is demonstrated on two cases: for the design of a half-bridge amplifier and for a fully differential BTL class-D loop filter topology that achieves less than 0.003% THD at 680 mW output power in typical 0.18 μm CMOS technology.
