This Special Issue of AEU International Journal of Electronics and Communications is devoted to the 2023 edition of the International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD 2023), which was held in Funchal, Madeira Island, Portugal, from the 3rd to the 5th of July 2023.
SMACD has become the reference forum devoted to modeling, simulation and synthesis for analog, mixed-signal, radio frequency and multi-domain integrated circuits and systems, as well as emerging technologies and applications. Open-source tools and methods for integrated circuit design and experiences with modeling, simulation, and synthesis techniques in diverse application areas are also covered.
SMACD 2023 received more than 100 submissions from all over the world. The conference program included the participation of two keynote speakers and 65 selected papers distributed among 12 thematic sessions. The program also included a PhD Competition on Electronic Design Automation (EDA) with live demonstrations, and, for the first time, an IC Design Contest.
This special issue of AEU International Journal of Electronics and Communications aims at publishing extended versions of top-ranked papers in the conference. The papers invited to contribute to this special issue were subjected to a standard peer-review process by outstanding researchers in the field. We are very grateful to them for their hard work and valuable suggestions.
The SMACD 2023 papers selected for this issue are summarized as follows.
In the first paper, “Automated Design Flow for Synthesizable ADPLL: From Specification to GDS” Kwon and Wentzloff adopt a cell-based architecture for a synthesizable all-digital phase-locked loop (PLL) generator. The all-digital architecture enables the use of a theory-based frequency domain model for predicting the output specifications once the oscillator performance is characterized. Based on the oscillator performances, the PLL specifications can be predicted. The phase noise performance of the PLL is estimated by applying noise transfer functions to each noise source. The combination of human-knowledge-based modeling and implementation using existing digital synthesis tools significantly reduces the time for characterization and design. One of the synthesized PLLs was fabricated as part of a fully-synthesized SoC and the measurement results are compared to the predicted values.
The second paper, entitled “GPU versus FPGA implementation of a digital predistortion linearizer for wideband radiofrequency power amplifiers” by Li, Montoro and Gilabert, deals with the implementation of digital predistortion linearizers for wideband power amplifiers. Digital predistortion is initially explored with high-level platforms for benchmarking using behavioral models. Once the optimum configuration is found, the hardware implementation is addressed using a hardware-in-the-loop approach. Graphic processing units (GPUs) and field programmable gate arrays (FPGAs) are capable to meet the high throughput requirements for linearizing the power amplifiers dealing with current 5G wideband signals. Both implementation platforms are considered and compared in terms of hardware resources usage, precision, throughput and linearization performance.
The third paper, “An area efficient inductorless super-regenerative receiver front-end for biomedical implant devices” by Pekcokguler, Dündar and Dehollain, proposes a novel area and energy efficient inductorless superregenerative receiver (SRR) for medical implants dedicated to patient continuous monitoring. The focus of this work is brain implants, especially used for epilepsy monitoring and treatment. Medical implants must operate with ultra-low power to prevent surgical interventions for maintaining normal operation of the devices. The most power consuming block in the implants is the RF radio, and local oscillator is the biggest contributor to the total power consumption. Super-regenerative receiver (SRR) architecture offers a solution to decrease the power consumption by quenching the oscillator and using its start-up transient to regenerate received weak signal. The proposed SRR was fabricated in a 180 nm CMOS technology. The proposed architecture achieves an order of magnitude area reduction with respect to competing approaches.
In the fourth paper, “In-depth Multi-Objective charge pump design space exploration towards the automatic synthesis of power management units”, Santos, Fernandes, Santos and Martins present a mixed-signal design flow whose purpose is to automatically produce, from the system-level to the ready-for-tape-out layout, complex power management units (PMUs) when given a set of specifications. Particularly, an academic electronic design automation tool is adapted and applied to explore the performance boundaries of a charge pump required in a state-of-the-art PMU in a 180-nm technology process and determine the optimal tradeoffs between performance and the, severely constrained, layout area. Worst-case corner optimization on many-dimensional design and performance spaces produced tens of design solutions that provide a thorough analysis between worst-case efficiency, voltage drop, and rise and fall times, impossible to perform in the manual design. The obtained insights on the design space were used to speed-up the process of devising a solution for tape-out.
The fifth paper, “Reliability improvement of SRAM PUFs based on a detailed experimental study into the stochastic effects of aging” by Santana-Andreo, Saraza-Canflanca, Castro-Lopez, Roca and Fernandez, deal with the effects of aging on physical unclonable functions (PUFs) based on SRAMs. The SRAM-based PUF uses the unpredictable power-up value of the cells within an SRAM. Although these values should ideally be always the same within each SRAM to accomplish a correct PUF operation, this is often not the case, especially when factors like circuit aging are considered. In this paper, a detailed experimental characterization of the nature of aging in SRAM PUFs is reported, demonstrating that the impact of non-conductive hot-carrier injection cannot be neglected. It is also shown that different cells degrade differently, highlighting the importance of accounting for the stochasticity of aging. After that, an experimental method is presented to select the cells with the most stable power-up response is introduced. Using these cells results in a more stable response, and thus a better PUF performance.
The sixth paper, “RapidIP—Automated design of a 220–260 GHz power amplifier in a 130 nm BiCMOS technology”, is an extended version of a work that won the 2023 SMACD EDA Competition. In it, Bierbuesse, Dietrich, Heidebrecht and Negra tackle the automated design of a power amplifier. The applied approach enables the evaluation of thousands of different topologies in a matter of minutes. Post-layout simulation results offer competitive performances with respect to the state-of-the-art of power amplifiers in similar frequency bands.