Functional Validation of the RISC-V Unlimited Vector Extension
Fernandes, A.
; Crespo, E.
;
Neves, N.
; Tomás, P.
; Roma, N
;
Falcão, G.
IEEE Embedded Systems Letters Vol. 17, Nº 1, pp. 2 - 5, February, 2025.
ISSN (print): 1943-0663
ISSN (online): 1943-0671
Scimago Journal Ranking: 0,43 (in 2024)
Digital Object Identifier: 10.1109/LES.2024.3416820
Download Full text PDF ( 334 KBs)
Downloaded 1 time
Abstract
Data streaming and data-flow computing paradigms have been on the rise, aiming to improve the performance of general-purpose processors. However, providing support for data streaming typically requires the definition of new instruction set architecture (ISA) extensions, which must be thoroughly validated before being implemented in hardware. This step is usually carried out using instruction set simulators (ISSs), to which the necessary streaming support must be added. Accordingly, this work proposes a new validation simulator for the recently presented stream-based RISC-V ISA unlimited vector extension (UVE). The proposed tool is based on Spike, the golden reference instruction set simulator ISS for RISC-V extensions. It is capable of processing a wide range of memory access patterns and provides the necessary mechanisms to validate the target extension, as well as to evaluate the resulting instruction reduction gains.
