Power optimisation of both a high-speed counter and a retiming element for 2.4 GHz digital PLLs
Electronics Letters Vol. 54, Nº 4, pp. 284 - 285, March, 2018.
ISSN (print): 1350-911X
ISSN (online): 0013-5194
Scimago Journal Ranking: 0,41 (in 2018)
Digital Object Identifier: 10.1049/el.2017.4391
he power optimisation at circuit level of a high-speed counter and a retiming circuit aimed for ultra-low-power digital phase-locked-loops (PLLs) is presented. The high-speed counter topology is based on a well-known asynchronous type with a precise sampling phase generator. Different types of custom true single-phase clock (TSPC) logic style are briefly revised and then strategically used. It is shown that a particular TSPC flip-flop when operating as a retiming element can achieve optimal power efficiency. A prototype was fabricated in an earlier generation 0.13 μm CMOS technology and characterised with a 1 V supply. Measurements show a state-of-the-art power consumption of about 48 μW when operating with a 2.4 GHz input signal.