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Logarithmic AD Converter with Selectable Transfer Characteristic

Mauro, M. ; Horta, N. ; Guilherme, J.G.

IEEE Transactions on Circuits and Systems II: Express Briefs Vol. 63, Nº 3, pp. 234 - 238, March, 2016.

ISSN (print): 1558-3791
ISSN (online): 1549-7747

Scimago Journal Ranking: 0,54 (in 2016)

Digital Object Identifier: 10.1109/TCSII.2015.2503567

This paper presents a logarithmic analog-to-digital converter architecture with selectable transfer characteristic. A delay-matched regeneration detection circuit and the transfer characteristic selection method are also presented. The transfer characteristic selection can be used to improve both resolution and INL of the converter for larger input voltages. A transistor level implementation, using the UMC 130nm design process, was simulated to confirm the feasibility of the proposed architecture described in this paper.