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Single-Stage Amplifier biased by Voltage-Combiners with Gain and Energy-Efficiency Enhancement

Póvoa , R. P. ; Lourenço, N. ; Martins, R. M. ; Canelas, A. ; Horta, N. ; Goes, J.

IEEE Transactions on Circuits and Systems II: Express Briefs Vol. PP, Nº 99, pp. 1 - 1, March, 2017.

ISSN (print): 1558-3791
ISSN (online): 1549-7747

Scimago Journal Ranking: 0,76 (in 2017)

Digital Object Identifier: 10.1109/TCSII.2017.2686586

This paper presents the design of a single-stage amplifier with enhanced gain and speed, without the need of using any cascode devices, positive-feedback or feed-forward technique. Instead, two voltage-combiners replace the traditional tail current-source, commonly employed to bias the differential-pair. The resultant topology shows both additional DC gain and a gain-bandwidth product enhancement. Simulation results of a properly optimized circuit, using AIDA-C, a state-of-the-art multi-objective multi-constraint IC sizing and optimization tool, demonstrate that a DC gain above 47dB and a figure-of-merit better than 960MHz*pF/mA, in corner conditions, can be achieved with this topology, in the UMC 130nm technology. The circuit was fabricated and experimentally measured, showing an energy-efficiency figure-of-merit of 1023.6MHz*pF/mA.