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A Fully Parallel Architecture for Designing Frequency-Agile and Real-Time Reconfigurable FPGA-Based RF Digital Transmitters

Dinis, DACD ; Cordeiro, R. ; Oliveira, A. ; Vieira, J. ; Silva, TOS

IEEE Transactions on Microwave Theory and Techniques Vol. 66, Nº 3, pp. 1489 - 1499, March, 2018.

ISSN (print): 0018-9480
ISSN (online):

Journal Impact Factor: 2,711 (in 2008)

Digital Object Identifier: 10.1109/TMTT.2017.2764451

Real-time frequency agility is one of the key limitations of current all-digital transmitters (ADTs). In this paper, to address this problem, an ADT based on direct-RF generation is proposed and implemented in a field-programmable gate array (FPGA). To achieve this, the pulse encoding is performed after the digital upconversion, which presents challenges in the pulse encoder implementation. However, the proposed design considerably improves the frequency agility when compared with current state-of-the-art approaches. Two different pulse encoders were designed in this paper, one is based on pulsewidth modulation (PWM) and the other on delta-sigma modulation (ΔΣM). These units are implemented with high parallelization to achieve the required equivalent sampling rates. The proposed design enables the implementation of all-digital RF transmitters in FPGA with a widely tunable carrier frequency. In this paper, a variation from 0.1 up to 6 GHz of carrier frequency, with a maximum frequency resolution of 1.5625 MHz, is demonstrated. Measurement results in terms of signal-to-noise ratio (SNR) and error-vector magnitude are presented and discussed. In the case of the PWM, maximum SNRs of 39 and 36 dB were obtained for a 5 and 10 MBd of symbol rates (SRs). In the case of ΔΣM, maximum SNRs of 38 and 35 dB were obtained for 20 and 40 MBd of the SR.