A Survey on Programmable LDPC Decoders
; Sousa, L.
IEEE Access Vol. 4, Nº 4, pp. 6704 - 6718, July, 2016.
ISSN (print): 2169-3536
ISSN (online): 2169-3536
Journal Impact Factor: 1,270 (in 2015)
Digital Object Identifier: 10.1109/ACCESS.2016.2594265
Low-density parity-check (LDPC) block codes are popular forward error correction schemes due to their capacity approaching characteristics. However, the realization of LDPC decoders that meet both low latency and high throughput is not a trivial challenge. Usually, this has been solved with ASIC and FPGA technology that enables meeting the decoder design constraints. But the rise of parallel architectures, such as graphics processing units, and the scaling of CPU streaming extensions, has shown that multi-core and many-core technology can provide a flexible alternative to the development of dedicated LDPC decoders for the compute-intensive prototyping phase of the design of new codes. Under this light, this paper surveys the most relevant publications made in the past decade to programmable LDPC decoders. It looks at the advantages and disadvantages of parallel architectures and data-parallel programming models, and assesses how the design space exploration is pursued regarding key characteristics of the underlying code and decoding algorithm features. The paper concludes with a set of open problems in the field of communication systems on parallel programmable and reconfigurable architectures.