In this paper, the concept of hierarchical multi-objective optimization is applied to analog integrated circuit placement automation, where current-flow and current-density considerations are taken to improve the reliability and, reduce post-layout routing-induced parasitics of the circuit. The current-flow constraints are satisfied by forcing a monotonic routing directly in an absolute placement representation, while the impact of current-intensive interconnects is mitigated with the electromigration-aware optimization of the optimal wiring topology for all nets of the circuit. The problem’s complexity is reduced using the hierarchy in the circuit’s partitions, combining, bottom-up, Pareto fronts of placements that explore the tradeoffs between the design objectives. The approach is demonstrated in analog circuit structures for the United Microelectronics Corporation 130nm design process. Post-layout simulations show the importance of considering both current-flow and current-density considerations for an effective fully-automatic placement.