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AIDA: Layout-aware analog circuit-level sizing with in-loop layout generation

Lourenço, N. ; Martins, R. M. ; Canelas, A. ; Póvoa , R. P. ; Horta, N.

Integration, the VLSI Journal Vol. 55, Nº 09, pp. 316 - 329, September, 2016.

ISSN (print): 0167-9260
ISSN (online):

Scimago Journal Ranking: 0,22 (in 2016)

Digital Object Identifier: 10.1016/j.vlsi.2016.04.009

This paper presents AIDA, an analog integrated circuit design automation environment, which implements a design flow from a circuit-level specification to physical layout description. AIDA results from the integration of two in-house tools, namely, AIDA-C and AIDA-L. AIDA-C consists of an innovative layout-aware optimization-based methodology for automatic sizing of analog ICs. AIDA-L, the layout generator, implements a fully automated layout generation methodology. AIDA-L provides two alternative floorplanners, a template-based and an optimization-based. The placed modules, whose layouts are spawned by the in-house module generator, are fed together with the node electric-currents to the electromigration-aware multi-port Router that finalizes the layout. Finally, the integration of AIDA environment on the traditional analog IC design flow is discussed, and demonstrated for analog IC sizing and layout generation. Results are validated by industrial simulators and analysis tools, such as, HSPICE®, SPECTRE®, ELDO® or CALIBRE®.