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A parallel architecture for real-time video coding

Faria, S.M.M. ; Assunção, P.A. ; Perdigão, F. ; Silva, V. ; Sá, L. V.

Microprocessing and Microprogramming (EUROMICRO) Vol. 30, Nº 1-5, pp. 439 - 445, August, 1990.

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Digital Object Identifier: 10.1016/0165-6074(90)90280-M

A computing architecture capable of coding video signals in real time is described. The codec uses several digital signal processors (DSPs) which can be easily programmed to implement the recent H.261 algorithm approved by the CCITT. The DSPs are organized as a single instruction multiple data (SIMD) computing architecture. Every image in a sequence is divided in regions of horizontal strips and each region is operated by its own processor. The principle is used in both the encoder and decoder. These local processors code (decode) one horizontal strip of data which, using the terminology of the H.261 norm, corresponds to two group of blocks (GOBs). They also communicate to a central processor which multiplexes (demultiplexes) the coded data from (for) the processors in the encoder (decoder). In the case of the encoder this central processor also controls a data buffer for bit-rate adaptation. Lateral communication between adjacent processors is also permitted. This allows comparisons between blocks situated in neighbouring regions, as required by most motion estimation algorithms.