Creating and sharing knowledge for telecommunications

Embedded Architectures for LDPC Decoding

Falcão, G. ; Sousa, L. ; Silva, V.

Embedded Architectures for LDPC Decoding, Proc International Conf. on Embedded Computer Systems: Architectures, Modeling and Simulation - SAMOS, Samos, Greece, Vol. 1, pp. - , July, 2010.

Digital Object Identifier:

Abstract
Recently, the development of LDPC decoding solutions has been proposed for a vast set of architectures, ranging from hardware dedicated (VLSI, FPGA) to fully programmable ones (GPU, Cell/B.E.). In this paper we propose an efficient embedded multicore architecture able of performing real-time LDPC decoding. We analyze the main characteristics necessary to achieve a given throughput, and we validate our proposal by using the popular Cell/B.E. architecture from Sony/Toshiba/IBM, which relates very closely with the one here propose. Finally, we compare related art for LDPC decoding on GPUs, ASICs and FPGAs.