A Study on CMOS Time Uncertainty with Technology Scaling
A Study on CMOS Time Uncertainty with Technology Scaling, Proc International Workshop on Power and Timing Modeling, Optimization and Simulation - PATMOS, Lisbon, Portugal, Vol. 0, pp. 0 - 0, September, 2008.
Digital Object Identifier:
This paper evaluates the clock generation quality of different digital circuits associated with clock generation and distribution. Circuit's noise response, jitter, and uncertainty are evaluated for different noise sources and loading conditions. We present performance simulations for inverters and inverter chains implemented in different technologies from AMS and UMC foundries. We show that the device size-scaling trend is increasing the uncertainty associated with this circuits, decreasing their precision. The correlation between circuit's parameters and selected performance metrics is also highlighted.