State-of-the-art layout-aware synthesis methods for analog integrated circuits (ICs) rely extensively on off-the-shelf layout extractions and post-layout simulations to assess the circuits’ functional behavior, incurring prohibitive optimization times. To address this challenge, this paper proposes the development of a novel post-layout performance regressor based on deep learning (DL) models. Specifically, convolutional variational autoencoders (CVAEs) are applied for unsupervised feature extraction from analog layouts, producing a latent space. Then, a collection of artificial neural networks (ANNs) conducts performance estimation directly from the lower-dimensional space. By the usage of convolutional layers to deal with analog IC layouts, the model learns the underlying impact of the floorplan and interconnects and over the functional behavior of the circuit. Preliminary results reveal mean absolute percentage errors (MAPEs) below 2% for different performance metrics of a typical analog structure, with the model inference requiring only 3.9 milliseconds, about 3,000× faster than the bypassed full parasitic extraction and simulation.