Automatic simulation-based sizing approaches are essential in designing radio-frequency (RF) integrated circuit (IC) blocks for modern applications. However, optimizations considering process, voltage, and temperature (PVT) corners or layout still pose unprecedented challenges in applying these tools due to the high simulation times and different simulator convergence issues. This paper proposes two different deep learning (DL) models to assist the PVT-inclusive simulation-based sizing process of RF ICs, and more specifically, voltage-controlled oscillators (VCOs). Given specific devices’ dimensions, the 1st model classifies the likeability of the circuit to convergence for nominal and PVT corners, bypassing solutions that will hardly procedure valuable information for the optimization process, while the 2nd model predicts the VCOs’ oscillating frequencies for the aforementioned conditions. The methodology is tested on a state-of-the-art VCO, reducing 19% of the workload of the circuit simulator, ultimately saving almost 5 days of computational effort and with improvement on the optimization result.