At advanced integration nodes, the impact of layout-dependent effects (LDEs) turn the performance of MOSFET devices strongly dependent on the layout implementation details, but also, of its surrounding neighborhood. However, in the traditional design flow, the real LDEs-impact is only known after complete extraction and post-layout simulation, causing re-design iterations with no valuable feedback information to fix the problem. This paper proposes an automatic placement methodology for analog integrated circuit (IC) layout design, that minimizes the mobility and threshold-voltage-related variations caused by the two major sources of LDEs above the 40 nm technology nodes, i.e., well-proximity effect and length of oxide diffusion. An absolute representation of the floorplan is adopted, and, a multi-objective optimization (MOO) algorithm with LDE-impact mitigation operators, is applied. Established LDE formulations used in BSIM models are used to guide placement optimization, shorting the gap between pre and post-layout performance.