In this paper, the use of machine learning techniques
to repurpose already available Pareto optimal fronts of analog
integrated circuit blocks for new contexts (loads, supply voltage,
etc.) is explored. Data from previously sized circuits is used to train
models that predict both circuit performance under the new
context and the corresponding device sizes. A two-model chain is
proposed, where, in the first layer, a multivariate polynomial
regression estimates the performance tradeoffs. The output of this
performance model is then used as input of an artificial neural
network that predicts the device sizing that corresponds to that
performance. Moreover, the models are trained with optimized
sizing solutions, leading almost instantly to predicted solutions that
are near optimal for the new context. The proposed methodology
was integrated into a new framework and tested against a real
circuit topology, with promising results. The model was able to
predict wider and, in some cases, better, performance tradeoff,
when compared to independent optimization runs for the same
context, despite requiring 400 times fewer circuit simulations.