11.7b Time-To-Digital Converter with 0.82ps resolution in 130nm CMOS Technology
Guilherme, J.G.
; Granja, R.
; Mauro, M.
;
Horta, N.
11.7b Time-To-Digital Converter with 0.82ps resolution in 130nm CMOS Technology, Proc IEEE PhD. Research in Microelectronics and Electronics - PRIME, Prague, Czech Republic, Vol. , pp. - , July, 2018.
Digital Object Identifier: 10.1109/PRIME.2018.8430374
Abstract
This paper describes a high-resolution 11.7b Time-
to-Digital Converter (TDC) designed in a pure digital CMOS
130nm technology. The target architecture comprises a looped
delay-line based on an inverter-based pulse-shrinking technique.
The proposed technique can achieve a 0.82ps resolution with a
dynamic range of 2.918ns, an integral nonlinearity (INL) of -2.4
to 2.11 and a differential nonlinearity (DNL) of -0.91 to 0.87 LSB.
In addition, it occupies a low area of 0.148 mm 2 .
