In this paper, deep learning and artificial neural networks (ANNs) are used to size analog integrated circuits. In classical optimization-based sizing strategies the computational intelligent techniques are used to iterate over the map from devices sizes to circuits' performances, provided by design equations or circuit simulations, whereas here, it is performed an exploratory work on how ANNs can be capable of solving analog integrated circuit sizing as a direct map from specifications to the sizing. The proposed methodology was implemented and tested on a real circuit topology, with promising results. Moreover, trained ANNs were able to extend the circuit performance boundaries outside the train/validation set, showing that more than a mapping for the training data, the model is capable of learning reusable design patterns and provide promising designs.