This paper presents an architecture employing latched comparators and a time-to-digital converter to perform a logarithmic analog-to-digital conversion. Latched comparators are used to sample the input and reference signals and convert them to a time domain representation. A time-to-digital converter is then used to obtain the digital output word. The presented architecture eliminates input independent delays from the final quantization result. A transistor level implementation was simulated to confirm the feasibility of the architecture described in this paper. Monte Carlo and process corner simulation results are presented which confirms the feasibility of the architecture presented.