A 50MHz+ bandwidth real-time FPGA implementation of OFDM-based PHY transceiver for 5G
A 50MHz+ bandwidth real-time FPGA implementation of OFDM-based PHY transceiver for 5G, Proc Wireless Innovation Forum SDR WInnComm, Washigton, United States, Vol. 1, pp. 1 - 8, March, 2016.
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This paper introduces a fully pipelined implementation architecture for OFDM-based transceivers that moves one step closer to fulfilling the envisioned 5G bandwidth demands. The implementation uses high level abstraction tools to develop and test the algorithms, significantly increasing the productivity and reducing costs and time-to-market. The proposed architecture defines a common interface between blocks, with FIFOs interconnecting the blocks and a soft-handshake, which present significant advantages over the other reported architectures.
The proposed architecture is implemented in a fully working real-time platform, using COTS FPGA and RF development boards. The demonstrator has a real-time scalable bandwidth from 20MHz to 54MHz. Using 64-QAM modulation and 1024 carriers, the implementation attains over 300Mbits/s of raw bitrate in each direction, using less than one quarter of the FPGA resources.