A new Table Based Modelling of 28nm Fully Depleted Silicon-On Insulator (FDSOI)
Mahmoud , A.
A new Table Based Modelling of 28nm Fully Depleted Silicon-On Insulator (FDSOI), Proc IEEE International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Lisbon, Portugal, Vol. 1, pp. 1 - 4, June, 2016.
Digital Object Identifier: doi: 10.1109/SMACD.2016.7520746
In this work, a multivariate interpolation lookup tables (LUTs) model for nanometer CMOS transistors is presented. A novel lookup-table (LUT) method, which is based on a multivariate Neville's algorithm for the current-voltage (I-V) and Capacitance-voltage (C-V) characteristics of a transistor, is proposed for the simulation of MOS transistor circuits. The simulation speed is noted to be significantly enhanced with sufficient accuracy via a dynamic programming procedure with the implementation of the proposed approach compared to the current state of the art models. Simulation results are implemented in a 28-nm fully depleted SOI technology (FDSOI). Compared to simulations with both the BSIMSOI model and the Lagrange interpolation lookup table, the computation time of the proposed approach can be reduced by 8.X and beyond in transient analysis.