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Thermal-aware floorplanning and layout generation of MOSFET power stages

Guilherme, J.G. ; Horta, N.

Thermal-aware floorplanning and layout generation of MOSFET power stages, Proc IEEE International Symp. on Circuits and Systems - ISCAS, Lisbon, Portugal, Vol. 1, pp. 1 - 4, May, 2015.

Digital Object Identifier: 10.1109/ISCAS.2015.7169135


This paper presents a thermal-aware floorplaning tool for integrated MOSFET power stages. It generates area and power optimized transistors, automatically complying with design rules. The tool also creates placement solutions of power stages, optimizing for area, wire-length and temperature spread. The tool creates technology independent layouts, and directly export designs into GDSII format, allowing complete independence from IC design platforms. A brief comparison of floorplanning techniques, embedded in this tool, is presented for several generally known benchmarks. The device layout and thermal-aware floorplaning capabilities are demonstrated and compared with manual designs of a half-bridge power stage for a Class-D amplifier, and a manually optimized device layout in a DC-DC buck converter stage - the tool results exhibit lower resistance and dynamic power losses while speeding-up the design flow by orders of magnitude.