SCALES: A high speed simulator tool for pipeline A/D converters
Silva, C.
;
Guilherme, J.G.
;
Horta, N.
SCALES: A high speed simulator tool for pipeline A/D converters, Proc International Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Lisbon, Portugal, Vol. 1, pp. 1 - 4, June, 2016.
Digital Object Identifier: 10.1109/SMACD.2016.7520751
Abstract
This paper presents the latest version of the
pipeline ADC simulator tool (SCALES), a high speed analog
behavior simulation tool for analog-to-digital converters.
This tool allows topology selection and the digital calibration
of the main frontend blocks. Additionally, the tool generates
also the required Verilog code to implement the digital
calibration block. Several block non-linearities are included
in the simulation, such as gain and offset errors, capacitor
mismatch, thermal noise, parasitic capacitances, settling
errors and other important error sources. The tool has been
used and validate in several high performance pipeline
ADCs, up to 16 bits resolution.
