From Low-architectural Expertise Up to High-throughput Non-binary LDPC Decoders: Optimization Guidelines using High-level Synthesis
; George, N.
; Karras, K.
; Novo, D. N.
; Ienne, P. I.
From Low-architectural Expertise Up to High-throughput Non-binary LDPC Decoders: Optimization Guidelines using High-level Synthesis, Proc International Conf. on Field Programmable Logic and Applications - FPL, London, United Kingdom, Vol. 1, pp. 1 - 8, September, 2015.
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HLS tools have been introduced with the promise
of easening and shortening the design cycle of tedious and
error-prone RTL-based development of hardware accelerators.
However, they do so either by concealing meaningful hardware
decisions which model the computing architecture—such as
OpenCL compilers—or by abstracting them away into a high-
level programming language—usually C-based. In this paper,
we show that although Vivado HLS is sufficiently mature to
generate a functionally correct FPGA accelerator from a naive
description, reaching an accelerator which optimizes the FPGA
resource utilization in a way that conveys maximum performance
is a process for a hardware architect mindset. We use a highly
demanding application, that requires real-time operation as a
requirement, and develop a non-binary LDPC decoder on a state-
of-the-art Virtex 7 FPGA, using the Vivado HLS framework.
Despite using the same programming syntax as a C-language
software compiler, the underlying programming model is not the
same, thus, the optimizations required in code refactoring are
distinct. Moreover, directive-based optimizations that tweak the
synthesized C description hardware must be used in order to
attain efficient architectures. These processes are documented in
this paper, to guide the reader on how an HLS-based accelerator
can be designed, which in our case, is shown to reach more than
half the performance achieved with dedicated hand-made RTL