This paper presents a digital low-IF Gaussian frequency-shift keying (GFSK) demodulator. The demodulator is based on a phase-shift quadrature discriminator. However, a preamble detector and a central control block improve significantly the demodulator total power consumption. An IF input signal of 1 MHz is used, the same of the data rate, hence, allowing a low-power receiver implementation. A digital implementation in a 130 nm process allowed a low silicon area of 0.06mm2. Simulations show a state-of-art current consumption of about 143 µA from a single 1.2 V supply voltage. The proposed demodulator requires a SNR of 15dB for a BER of 0.1% for up to ±200 kHz frequency offset variation.