On the Performance of LDPC and Turbo Decoder Architectures with Unreliable Memories
; Vosougui, A. V.
; Wang, G. W.
; Karakonstantis, G. K.
; Burg, A. B.
; Cavallaro, J. R. C.
On the Performance of LDPC and Turbo Decoder Architectures with Unreliable Memories, Proc Asilomar Conf. on Signals, Systems, and Computers, Pacific, United States, Vol. 1, pp. 1 - 1, November, 2014.
Digital Object Identifier: 0
In this paper, we investigate the impact of faulty
memory bit-cells on the performance of LDPC and Turbo channel
decoders based on realistic memory failure models. Our study
investigates the inherent error resilience of such codes to potential
memory faults affecting the decoding process. We develop two
mitigation mechanisms that reduce the impact of memory faults
rather than correcting every single error. We show how protection
of only few bit-cells is sufficient to deal with high defect rates.
In addition, we show how the use of repair-iterations specifically
helps mitigating the impact of faults that occur inside the decoder