In this paper, we present a real-time testbed Orthogonal Frequency Division Multiplexing (OFDM) signaling scheme. The testbed is implemented in a Field- Programmable Gate Array (FPGA) through Xilinx System Generator for DSP and includes all the blocks needed for the transmission path of OFDM. Time-domain synchronization is achieved through a joint maximum likelihood (ML) symbol- time and carrier frequency offset (CFO) estimator through the redundant information contained in the cyclic prefix (CP). Results show that a rough implementation of the signal path can be implemented by using only Xilinx System Generator for DSP. This work presents a valid FPGA implementation of an OFDM receiver synchronization algorithm using a high-level design tool.