This paper presents a new approach to enhance a state-of-the-art layout-aware analog IC circuit-level optimizer, by embedding statistical knowledge from an automatically generated gradient model into the multi-objective multi-constraint optimization kernel based on a modified NSGA-II algorithm. The gradient model is automatically generated by, first, using a design of experiments (DOE) approach with two alternative sampling strategies, the full factorial design and the fractional factorial design, which define the samples that will be accurately evaluated using a circuit simulator (e.g. HSPICE®), second, extracting and ranking the contributions of each design variable to each performance measure or objective, and, finally, building the model based on series of gradient rules. The gradient model is then embedded into the modified NSGA-II optimization kernel, by acting on the mutation operator. The approach was validated with typical analog circuit structures for an industry standard 0.13 µm integration process, showing that, by enhancing the circuit sizing evolutionary kernel with the gradient model, the optimal solutions are achieved, considerably, faster and with identical or superior accuracy.