Performance Analysis of Low-Complexity VDLL Architectures for GNSS Signals
Performance Analysis of Low-Complexity VDLL Architectures for GNSS Signals, Proc European Navigation Conf. - ENC-GNSS, London, United Kingdom, Vol. 1, pp. 1 - 13, November, 2011.
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A simplified Vector Delay Lock Loop (VDLL) architecture is proposed for low-cost Global Navigation Satellite
System (GNSS) receivers operating with several satellite constellations in slow dynamics scenarios. The algorithm
propagates iteratively the estimated space/time trajectory through a grid of cells using a Bayesian approach.
At each iteration a new grid is generated centered at the position/time previously estimated. Side information can
be easily incorporated by assigning different a priori probabilities to the cells.