Memory-Hierarchy-Aware Decoding of Structured LDPC Codes on GPUs
Memory-Hierarchy-Aware Decoding of Structured LDPC Codes on GPUs, Proc Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems - ACACES, Fiuggi, Italy, Vol. 1, pp. 219 - 222, July, 2011.
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New strategies for developing computationally intensive high-throughput decoders for irregular LDPC codes adopted by the DVB-S2 and WiMAX standards are proposed. These decoders are developed for manycore GPU architectures. The decoders for both standards are flexible and scalable and achieve the required minimum data throughputs. Global memory accesses are minimized through compact data structures that allow efficient representation of Tanner graphs to conveniently exploit the memory hierarchy of the system.