This paper presents an automated design methodology for continuous time loop-filters dedicated to Class-D amplifiers, aiming the optimization of both THD and noise. This methodology is based on a modified genetic algorithm kernel, and a set of performance rules that integrates both the topology selection and circuit sizing by automatically generating and sizing filter topologies to minimize the loop THD and noise, but replacing traditional and very long transient and steady-state simulations by fast AC evaluations. The evolutionary algorithm accepts any kind of Spice like simulator as its evaluation engine, multiple filter topology templates and a set of design constrains and fixed component values can be included on the process adding flexibility. The presented approach is demonstrated for the design of a fully differential BTL class-D loop filter topology that achieves less than 0.003% THD at 680mW output power while maintaining the base-band noise term below 4uVms.