In-Depth Design Space Exploration of 26.5-to-29.5-GHz 65-nm CMOS Low-Noise Amplifiers for Low-Footprint-and-Power 5G Communications Using One-and- Two -Step Design Optimization
Martins, R. M.
IEEE Access Vol. 9, Nº --, pp. 70353 - 70368, May, 2021.
ISSN (print): 2169-3536
Scimago Journal Ranking: 0,93 (in 2021)
Digital Object Identifier: 10.1109/ACCESS.2021.3078240
Download Full text PDF ( 3 MBs)
Downloaded 1 time
Low-noise amplifiers (LNAs) play a significant role in modern millimeter-wave (mmWave) integrated circuits for 5fth-generation (5G) communications systems. However, the proper analysis of their design tradeoffs that allow for a realistic topology comparison is impractical. The many conflicting specifications that must be carefully balanced make the problem intractable. In this paper, the 148-dimensional performance spaces of three 28-GHz LNAs are fully explored for a 65-nm CMOS technology node, using an enhanced electronic design automation tool. One- and two-step many-objective optimizations provide up to 1024 different LNAs for each of the considered topologies, enabling a thorough assessment of their performance tradeoffs. The first optimizes all the design parameters at once. In contrast, the latter optimizes the spiral inductors in a first step. Then, in a second step, it optimizes the remaining parameters. The resulting designs provide new insight on the tradeoffs between gain, noise figure, power, and circuit's footprint for current 5G specifications. Process, voltage, and temperature corners impact the LNAs' performance severely. Still, the optimization shows that proper sizing of these topologies compete with the most-recent mmWave LNAs and can play a role in the challenging 28-GHz band.