Combining Layer-Aware Images and Pre-Layout Fusion for Accurate Analog IC Post-Layout Performance Prediction
Almeida, C.A.
;
Azevedo, F. A.
; Oliveira, M. O.
;
Martins, R. M.
Combining Layer-Aware Images and Pre-Layout Fusion for Accurate Analog IC Post-Layout Performance Prediction, Proc IEEE International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Dresden, Germany, Vol. , pp. - , June, 2026.
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Abstract
Layout-aware analog/radio-frequency (RF) integrated circuit (IC) optimization is often bottlenecked by the computational cost of parasitic extraction and simulation. This work presents a technology-agnostic, image-driven pipeline that addresses two limitations of prior post-layout performance regressors: missing pre-layout functional behaviour priors and loss of layer semantics in grayscale rasterization. We introduce (i) pre-layout–aware fusion, concatenating standardized schematic level performance metrics with a convolutional variational autoencoder (CVAE) latent, and (ii) layer-aware RGB rasterization, mapping selected GDS layers to dedicated channels to preserve polarity and gate-geometry cues. On 10,192 layouts of a 65-nm Gm-C filter, the proposed methodology significantly improves post-layout prediction accuracy. Compared with the image-only baseline in [1], the proposed framework reduces the mean Gdc absolute error (MAE) from 4.694 dB to 1.184 dB and the offset MAE from 0.109V to 0.028V.
