The major goal of this project is to design, integrate in a 90nm CMOS technology and experimentally evaluate a calibration-free 2-channel time-interleaved 6-bit 1GS/s CMOS Pipeline ADC with an EE better than 0.2-0.3 pJ per conversion step and at the same time achieving a very low die area. Many novel techniques will be addressed to reach such goal such as, intensive use of passive structures, amplifier sharing, simple amplifier topology and exhaustive circuit optimization. A second aim of the project will be to include, on-chip, an efficient solution for providing built-in self-testing capability.
|Start Date: 01-09-2007|
|End Date: 01-03-2011|
|Team: Rui Fuentecilla Maia Ferreira Neves, Nuno Cavaco Gomes Horta|
|Groups: Integrated Circuits - Lx|
|Local Coordinator: Rui Fuentecilla Maia Ferreira Neves|
|Links: Internal Page|