| Acronym: ACTON |
| Main Objective: Complementary metal-oxide-semiconductor (CMOS) technologies provide unmatched digital compatibility and low-cost at a large production scale. Still, the design of millimeter-wavelength (mmWave) CMOS interfaces is mostly performed manually and struggles to reach the full potential allowable by the integration technologies. Furthermore, the severe impact of process variations or layout parasitics of deep nanometer nodes only further aggravates the design problem. Several electronic design automation (EDA) tools for radio frequency integrated circuit (IC) design have been proposed, however, as the operating frequency gradually ascends into the dozens of gigahertz, the application of existent tools to design modern mmWave interfaces results in prohibitive optimization cycles. In 2024, EDA solutions for mmWave IC design are highly needed, but still in an embryonic stage of development and application. Europe needs to take an early advantage and hold a leading position on the new market opportunities enabled by 5G and upcoming 6G networks, while, in parallel, thrive for technological independence. The main objective of the ACTON project is to decrease design time, errors and design costs of future deployments of 5G/6G IC interfaces; while, simultaneously, improving their performance, pushing them to the limits of advanced CMOS nodes. To do so, we propose exploratory research on the application of advanced artificial intelligence techniques, namely deep convolutional neural networks and generative adversarial networks, to mmWave structures. When combined with established EDA concepts and off-the-shelf computer-aided design tools for IC design, a design space beyond human capability will be explored and re-design iterations between electrical and physical design steps potentially eliminated. Within ACTON project, the proof of concept will be made by using the groundbreaking intelligent EDA (iEDA) tool to implement fundamental blocks of a 37-to-40-GHz (n260 band) transceiver (TRX), part of a cost-effective implementation of a phased-array front-end, intended to serve the next generation of 5G cellular deployments, including base stations, smartphones or tablets. |
| Reference: FCT/2023.11981.PEX |
| Funding: FCT |
| Start Date: 01-02-2024 |
| End Date: 31-07-2026 |
| Team: Ricardo Miguel Ferreira Martins, João Manuel Torres Caldinhas Simões Vaz, Luís Miguel Moreira Mendes, Nuno Cavaco Gomes Horta, Filipe Parrado de Azevedo, António Paiva Lapas de Gusmão, Rafael Alexandre Ascenso Vieira |
| Groups: Integrated Circuits - Lx, Wireless Circuits – Lx |
| Partners: Instituto de Telecomunicações |
| Local Coordinator: Ricardo Miguel Ferreira Martins |
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Associated Publications
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