Creating and sharing knowledge for telecommunications

Project: ECHO: error-correcting codes in high-performance communication systems through joint exploration of inference algorithms and parallel architectures

Acronym: ECHO
Main Objective:
Interference in communications can result in temporarily “blinding” the receiver, which can severely damage critical communications. This affects with particular gravity space and safety critical mobile applications. As a result new electronic equipments require the use of error correction codes. Low-density parity-check (LDPC) codes are sophisticated error correction schemes that have been explored to improve the accuracy of communications [1]. However, recent communication standards that incorporate these codes keep increasing the level of computational requirements. According to the ITU-T G.709 standards, optical communication systems [2] require extremely low error floors (below 10^(-15)) and higher throughputs (in the order of Gbit/s). This problem becomes even more critical for the powerful non-binary LDPC codes algorithms. Arriving at such low error rate requires running computationally complex simulations that could take months to execute [2] [3] on traditional processors (i.e., CPUs).

Given the complexity of these algorithms and standard requirements, it justifies the need for application acceleration (either for simulating and investigating new LDPC codes, or for final deployment of low-power architectures) through a proper choice of target devices, with application-specific performance considerations. The choice of the right device is a complex decision that involves considerations such as design time, application-level portability, customisability and performance indices such as speed, energy and silicon foot-print.

In this proposal our objective is to develop fast versions of belief-propagation algorithms, with a particlar focus in non-binary LDPC codes, and explore a subset of compute devices that have been proven to be efficient in the embedded computing domain, viz., field programmable devices and massively parallel processors. Within this proposal we search new solutions that optimise design time and energy efficiency, while accelerating communication algorithms.

Expected results of this cooperation:

- We expect to perform the dissemination of this collaboration through publications in tier-1 conferences (at least 5) and journals (at least 2), with high-impact publications both in the communications domain, as well as in the domain of electronic design automation.

- The highly optimised version of the algorithmic implementation will be considered to be patentable.

- Another goal of this collaboration is to perform joint supervisions of PhD students in both sides, merging the best skills of both teams and exploiting more efficiently the human resources available in both countries. All work here proposed shall be performed and developed by these PhD students.
Reference: Indo-Portuguese Programme for Cooperation in Science & Tecnology (FCT)
Funding: FCT
Start Date: 01-07-2017
End Date: 31-12-2023
Team: Gabriel Falcao Paiva Fernandes, Óscar Almeida Ferraz, Srinivasan Subramaniyan, Vitor Manuel Mendes da Silva
Groups: Multimedia Signal Processing – Co
Partners: Amrita University, India
Local Coordinator: Gabriel Falcao Paiva Fernandes

Associated Publications