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Project / GENERALISE

Project: Generative AI for Analog Chip Design

Acronym: GENERALISE
Main Objective:
This research proposal seeks to explore and develop generative AI techniques for chip design, with a focus on the potential of these techniques to optimize layout generation and device optimization while meeting specific design constraints. The goal of this research is to develop new generative models that can significantly reduce the time and cost of IC design, while also improving performance and efficiency.
Reference: SONY_AVGS
Funding: Sony Advanced Visual Sensing AG (Switzerland)
Start Date: 01-05-2023
End Date: 01-04-2026
Team: Nuno Calado Correia Lourenço, Ricardo Miguel Ferreira Martins
Groups: Integrated Circuits - Lx
Partners: Sony Advanced Visual Sensing AG
Local Coordinator: Nuno Calado Correia Lourenço

Associated Publications
  • Books1
  • P. E. Eid, F. A. Azevedo, N. Lourenço, R. M. Martins, Efficient Analog Integrated Circuit Sizing with GenAI: Exploring Generative Diffusion Models, Springer, Cham, Cham, 2025,
    | BibTex
  • 2Papers in Journals
  • P. E. Eid, F. A. Azevedo, N. Lourenço, R. M. Martins, Using denoising diffusion probabilistic models to solve the inverse sizing problem of analog integrated circuits, AEU - International Journal of Electronics and Communications, Vol., No., pp. 155767 - 155767, March, 2025 | BibTex
  • G. Liñán-Cembrano, N. Lourenço, N. Horta, J. de la Rosa, Design Automation of Analog and Mixed-Signal Circuits Using Neural Networks – A Tutorial Brief, IEEE Transactions on Circuits and Systems II: Express Briefs, Vol., No., pp. 1 - 1, October, 2023,
    | Abstract     | BibTex
  • 1Papers in Conferences
  • F. A. Azevedo, N. Lourenço, R. M. Martins, Late Breaking Results: Encoder-Decoder Generative Diffusion Transformer Towards Push-Button Analog IC Sizing, ACM/IEEE Design Automation Conference (DAC), San Francisco, United States, Vol., pp. -, June, 2025,
    | Abstract     | BibTex
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