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Project: Hierarchical Analog IC Automatic Synthesis

Acronym: HAICAS
Main Objective:
The HAICAS project addresses the lack of effective automation in AMS IC design once transistor-level simulations become too expensive for current state-of-the-art approaches. The project focus is on the research and development of new data-centric mechanisms, based on DL, to improve behavioral models with implementation-dependent transistor-level effects. In analogy, the proposed methods will work from schematic- to behavioral-level as parasitic extraction tools, when they bring the layout effects to the schematic-level. The advantage of the proposed modeling scheme when comparing to physical-centric manual modeling is that, given the improvements in computation and machine learning a data-centric approach will improve the generality of simplified behavioral models while maintaining their accuracy. By automating the models’ tuning to topology and technology parameters HAICAS enables the reuse of behavioral models between functional equivalent circuit topologies. Moreover, the proposed data-centric modeling can also describe analog ICs using lab measurements instead of simulation results. The implemented tool, AIDA-HL, will extend AIDA’s current bottom-up optimization to include behavioral simulation. Currently, AIDA supports a lower level for RF passive devices and an upper level with transistor-level spice simulation. In AIDA-HL, the new level of behavioral simulations, together, with the passing of simulation results between these levels of abstraction for on-the-fly model updates, will improve the usability of EDA tools for hierarchical AMS IC design. Finally, the research team is composed of experienced AMS IC designers and EDA tools’ developers working together to ensure that the developed methods are designer-oriented and integrated into AMS IC design workflow. Shortening the acceptance gap in analog EDA is of the utmost importance, as the reception of new automation tools by IC designers is habitually low.
HAICAS, addresses high priority R&D&I challenges (managing complexity and managing diversity) of the Systems and Components sector highlighted in the ECS SRA 2019 and the project results are expected to reduce the effort required to design analog blocks by 30 to 65%. Thus, new application ideas with special requirements can be realized quickly and in high quality. Consequently, optimized and highly effective application-specific AMS IP blocks can be implemented in a shorter time span. The main outputs of the project are: (1) New methods for automatic inclusion of spice-level effects on Verilog-A/AMS behavioral models; (2) AIDA-HL, an analog EDA tool supporting behavioral simulation of hierarchical circuits, and extends current bottom-up approach with integrated and automatic move of data from the transistor-level optimization of analog cells up the hierarchy, to the behavioral models; (3) Prove the concept with the design, optimization, and fabrication of a BLE transmitter for IoT.
Reference: UIDB/EEA/50008/2020
Funding: IT
Start Date: 01-05-2020
End Date: 30-04-2022
Team: Nuno Calado Correia Lourenço, João Manuel Torres Caldinhas Simões Vaz, Ricardo Miguel Ferreira Martins, Ricardo Filipe Sereno Póvoa, António Manuel Lourenço Canelas, Marco António da Mota Carvalho Silva Pereira, Gunhan Dundar, Engin Afacan
Groups: Integrated Circuits - Lx, Wireless Circuits – Lx
Partners: Boğaziçi University, Istanbul, Turkey, Kocaeli University, Kocaeli, Turkey
Local Coordinator: Nuno Calado Correia Lourenço
Associated Publications