Creating and sharing knowledge for telecommunications

Project / LAY(RF)^2

Project: Ready-to-Fabricate RF and mmWave Integrated Circuit Layouts

Acronym: LAY(RF)^2
Main Objective:
The LAY(RF)^2 proposes the research, development and test of highly accurate and efficient methods for the automation of radio frequency (RF) and millimeter wave (mmWave) integrated circuit (IC) building blocks. This will be achieved by bringing together the previous work from the involved research teams, and, the knowledge of its members in the areas of: analog, mixed-signal, RF/mmWave IC design in deep nanometer technologies; electronic design automation (EDA); physics and modeling of semiconductor devices; computational intelligence; and also, machine learning (ML). The starting point for LAY(RF)^2 project is AIDASoft, an EDA tool developed by the ICG-Lx research team on the course of several IT projects. However, the latest developments in RF/mmWave IC domains and technologies are bringing new and complex challenges that must be mandatorily incorporated within EDA tools functionalities. The proposed automatic layout-aware methodology with ready-to-fabricate prototypes in-the-loop will be the most complete EDA solution for RF and mmWave IC design to date. While providing fully-automatic functionalities based on advanced computational intelligent and ML techniques, its target is not to drive designers away from their current workspace, but instead, to exploit the full capabilities of well-known and established off-the-shelf CAD tools, i.e., circuit simulator, electromagnetic simulator, DRC, LVS checker, and, layout extractor. By automatically exploring the ready-to-fabricate post-layout design space, re-design iterations can be successfully eliminated, bringing RF/mmWave circuit blocks closer to a first-pass fabrication success as every structure required for tape-out is considered and balanced during the optimization process, ultimately: (1) decreasing design time; (2) reducing design costs; (3) decreasing errors; and, (4) achieving optimal or near-optimal circuit performances.
Reference: UIDB/EEA/50008/2020
Funding: IT
Start Date: 01-02-2020
End Date: 31-01-2022
Team: Ricardo Miguel Ferreira Martins, Fábio Moreira de Passos, Nuno Cavaco Gomes Horta, Nuno Calado Correia Lourenço, João Manuel Torres Caldinhas Simões Vaz, Marco António da Mota Carvalho Silva Pereira, Luís Miguel Moreira Mendes, Alexandra Sofia Martins de Carvalho, Marta Isabel Belchior Lopes, Pui-In Mak, Jun Yin, Javier Sieiro
Groups: Integrated Circuits - Lx, Wireless Circuits – Lx, Pattern and Image Analysis – Lx
Partners: Grup de Radiofreqüència, Universitat de Barcelona (ES), State-Key Laboratory of Analog and Mixed-Signal VLSI, FST-ECE Macau (CN)
Local Coordinator: Ricardo Miguel Ferreira Martins

Associated Publications
  • 3Thesis
  • Speeding-Up Complex RF IC Sizing Optimizations with a Process, Voltage and Temperature Corner Performance Estimator using Deep ANNs, Instituto Superior Técnico, MSc Student, Pedro José da Costa Diogo Caldinhas Vaz, Supervisor: R. M. Martins, Co-supervisor: N. Horta, fev-2021 - out-2021
  • ANN-based Floorplan Recommender for Large Analog IC Building Blocks with Multiple Topological Constraints Coverage, Instituto Superior Técnico, MSc Student, Pedro José Borges Alves, Supervisor: R. M. Martins, Co-supervisor: N. Horta, fev-2021 - out-2021
  • Accelerating Voltage-Controlled Oscillator Sizing Optimizations with a Convergence Classifier & Frequency Guess Predictor, Instituto Superior Técnico, MSc Student, João Luís Carreira Pich Domingues, Supervisor: R. M. Martins, Co-supervisor: N. Horta, fev-2021 - out-2021
© 2024, IT - Instituto de Telecomunicações | All Rights Reserved