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Project: DSRC 5,9GHz

Acronym: HEADWAY
Main Objective: Develop a DSCR 5,9GHz (Layers PHY & MAC) transceiver, FPGA based.
Reference: Po 1011
Funding: BIT/BRISA
Start Date: 01-01-2011
End Date: 01-12-2012
Team: João Nuno Pimentel da Silva Matos, Arnaldo Silva Rodrigues de Oliveira, Nuno Balula de Almeida, Tiago Miguel Valente Varum, Joaquim José de Castro Ferreira, Nelson Cardoso, Manuel Ventura
Groups:
Partners:
Local Coordinator: João Nuno Pimentel da Silva Matos
Links: Internal Page
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