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Project: DSRC 5,9GHz

Acronym: HEADWAY
Main Objective:
Develop a DSCR 5,9GHz (Layers PHY & MAC) transceiver, FPGA based.
Reference: Po 1011
Funding: BIT/BRISA
Start Date: 01-01-2011
End Date: 01-12-2012
Team: Joao Nuno Pimentel da Silva Matos, Arnaldo da Silva Rodrigues de Oliveira, Nuno Balula de Almeida, Tiago Miguel Valente Varum, Joaquim José de Castro Ferreira, Nelson Cardoso, Manuel Ventura
Groups:
Partners:
Local Coordinator: Joao Nuno Pimentel da Silva Matos
Links: Internal Page

Associated Publications
  • 1Papers in Journals
  • T. Varum, J. N. Matos, P. Pinho, R. Abreu, A. Oliveira, J.A. Alves, Microstrip Antenna Array for Multiband Dedicated Short Range Communications, Microwave and Optical Tech. Letters, Vol. 53, No. 12, pp. 2794 - 2796, December, 2011,
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  • 6Papers in Conferences
  • T. Varum, J. N. Matos, P. Pinho, Printed antenna for On-Board Unit of a DSRC System, IEEE AP-S/URSI International Symp., Spokane, United States, Vol., pp. 457 - 460, July, 2011,
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  • T. Varum, J. N. Matos, P. Pinho, R. Abreu, Microstrip antenna for vehicular communications with improved axial ratio band, Conf. on Telecommunications - ConfTele, Lisbon, Portugal, Vol., pp. 1 - 4, April, 2011,
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  • N. Almeida, J. N. Matos, J.A. Alves, A Front-End to Vehicular Communications, IEEE Region 8 EUROCON 2011 International Conf. on Computer as a Tool joint with the Conf. on Telecommunications, Lisboa, Portugal, Vol. 1, pp. 1 - 1, April, 2011,
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  • J. N. Matos, A. Oliveira, T. Meireles, N. F. Ferreira, P.M. Mar, D. C. Carona, A. Serrador Serrador, Emergent Vehicular Communications: Applications, Standards and Implementation, URSI Seminar of the Portuguese Committee, Lisboa, Portugal, Vol. 1, pp. 1 - 1, September, 2010,
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  • D. C. Carona, A. Serrador Serrador, P.M. Mar, R. Abreu, N. F. Ferreira, T. Meireles, J. N. Matos, J.A. Alves, A 802.11p prototype implementation, IEEE Intelligent Vehicles Symp. - IV, San Diego, United States, Vol. 1, pp. 1116 - 1121, June, 2010,
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    | Full text (PDF 816 KBs) | BibTex
  • P.M. Mar, R. Abreu, J. N. Matos, The IEEE 802.11p Physical Layer implemented in a FPGA for the DSRC 5.9GHz Project, Jornadas sobre Sistemas Reconfiguráveis - REC, Aveiro, Portugal, Vol. 1, pp. 1 - 1, February, 2010,
    | Abstract
    | Full text (PDF 57 KBs) | BibTex