Creating and sharing knowledge for telecommunications

TeamUp5G: Training the future European leaders in 5G technology

on 01-04-2019

... TeamUp5G (New RAN TEchniques for 5G UltrA-dense Mobile networks) is an MSCA Innovative Training Network (ITN) that has just started in 2019, led by Prof. Ana Garcia Armada, from UC3M, whose focus is ultra-dense small cell systems, an important component in future heterogeneous 5G networks (commercial deployment in 2020) and beyond. It considers aspects such as enhanced multi-antenna techniques, efficient backhaul/fronthaul, massive MIMO, communications in the millimetre wavebands and visible light communications, as well as spectrum sharing and aggregation to enhance system performance/QoS.

IT is one of the 18 institutions from academia and industry that compose this consortium. The research team of 15 young researches supervised by committed experts from the industry and academia will advance the state of the art with: a) the design of novel physical/link/medium access control algorithms and protocols to enhance capacity and user satisfaction; b) new dynamic spectrum management; and c) opportunistic optimization of radio resources and cognitive radio techniques, together with self-organization capabilities, with different levels of collaboration, and techniques and methodologies to save energy.

Both mobile broadband and IoT applications and traffic will be harmonized. The new developed techniques will be analyzed by simulation and prototyping and some show-cases (immersive video, drones) will be developed to illustrate the novelty and applicability of our ideas. The consortium will train the young researchers on how to contribute and will actively participate in the activities of standardization bodies. Both terrestrial cellular scenarios and HetNets with drone-small cells will be investigated.

Photo: Experts from the TeamUp5G MSCA ITN European Training Network (ETN) during the kick-off meeting in Madrid, in February 2019 [Photos courtesy from Raquel Perez Leal].

HAnDLE: Hardware Accelerated Deep Learning Framework

on 24-03-2019

... Recent advances in Deep Neural Networks (DNNs) provided important breakthroughs in many domains (medical diagnosis, autonomous driving, natural language processing) and are seen as the likely solution towards the development of next generation’s intelligent systems. This has been achieved by relying on deeper and sparse networks, by integrating new layer types and novel activation functions, and through new training methodologies. However, DNNs are characterized by long execution times, a problem which is expected to worsen as networks become more complex and less susceptible to GPU acceleration. To overcome this issue, a new scalable hardware accelerator is being developed by the HanDLE research team to support the execution of state-of-the-art DNNs using FPGA technology. It aims to alleviate the involved computational complexity and memory bandwidth; support new complex DNN layers and activation functions; as well as sparse and non-uniform neural networks. The envisaged solutions will be compared with state-of-the-art off-the-shelf alternatives regarding performance and energy-efficiency.

The HAnDLE project is funded by FCT and is coordinated by INESC-ID. Its research team includes researchers and professors of Instituto de Telecomunicações/UC (Gabriel Falcão), INESC-ID/IST (Nuno Roma, Leonel Sousa, Pedro Tomás), IT Lisbon (André Martins, Luís Alexandre) and several Portuguese corporations.

Photo: Google’s TPU processor for deep learning