Ricardo Filipe Sereno Póvoa

Ricardo Póvoa

Academic position:	Researcher
Joining date:	01-01-2012
Roles in IT:	Researcher
Thematic Line:	Basic Sciences and Enabling Technologies
Group:	Integrated Circuits - Lx

Email: Send Email
Address: IT – Lisboa
Instituto Superior Técnico - Torre Norte - Piso 10
Av. Rovisco Pais, 1
1049 - 001 Lisboa
Tel: +351 21 841 84 54

By Authors
By Institutions

Scientific Achievements

Degrees

PhD, Instituto Superior Técnico, 16-04-2018
MSc, Instituto Superior Técnico, 20-06-2013
Licenciatura, Instituto Superior Técnico, 21-07-2010

Expertise Topics

Integrated Circuits Design
Electronic Design Automation

Academic Activities

1Supervision of PhD theses

As Co-supervisor

A Tunable Front-End Receiver IC with High Energy-Efficiency for Biomedical Applications and Healthcare, PhD Student, Rafael Alexandre Ascenso Vieira, Defended 07-2024

Publications

2Books

R. Vieira, R. P. Póvoa, N. Lourenço, N. Horta, Tunable Low-Power Low-Noise Amplifier For Healthcare Applications, Springer International Publishing, Lisboa, 2021,
| BibTex
R. P. Póvoa, JG Goes, N. Horta, A New Family of Cascode-Free Amplifiers with High Energy-Efficiency and Improved Gain, Springer, Cham, Switzerland, 2019,
| BibTex

2Books Chapters

A. Canelas, R. M. Martins, R. P. Póvoa, N. Lourenço, J.G. Guilherme, N. Horta, Enhancing an Automatic Analog IC Design Flow by using a Technology-Independent Module Generator, Chapter in, Performance Optimization Techniques in Analog, Mixed-Signal, and Radio-Frequency Circuit Design, Mourad Fakhfakh, Esteban Tlelo-Cuautle, Maria Helena Fino, IGI global, Medical Information Science Reference, 2014
R. P. Póvoa, N. Lourenço, A. Canelas, R. M. Martins, N. Horta, Synthesis of LC-Oscillators using Rival Multi-Objective/Multi-Constraint Optimization Kernels, Chapter in, Performance Optimization Techniques in Analog, Mixed-Signal, and Radio-Frequency Circuit Design, Mourad Fakhfakh, Esteban Tlelo-Cuautle, Maria Helena Fino, IGI global, Medical Information Science Reference, 2014

17Papers in Journals

R. Vieira, F. Naf, R. M. Martins, N. Horta, N. Lourenço, R. P. Póvoa, A Tunable Gain and Bandwidth Low-Noise Amplifier with 1.44 NEF for EMG and EOG Biopotential Signal, Electronics, Vol. 12, No. 2592, pp. 1 - 17, June, 2023,
| Abstract | BibTex
A. Gusmão, R. P. Póvoa, N. Horta, N. Lourenço, R. M. Martins, DeepPlacer: A custom integrated OpAmp placement tool using deep models, Applied Soft Computing Journal, Vol. 115, No. 1, pp. 108188 - 108188, January, 2022,
| Abstract | BibTex
R. M. Martins, N. Lourenço, R. P. Póvoa, N. Horta, Shortening the gap between pre- and post-layout analog IC performance by reducing the LDE-induced variations with multi-objective simulated quantum annealing, Engineering Applications of Artificial Intelligence, Vol. 98, No. n/a, pp. 104102 - 104102, February, 2021,
| Abstract | BibTex
R. P. Póvoa, A. Canelas, R. M. Martins, N. Lourenço, N. Horta, JG Goes, A new family of CMOS inverter-based OTAs for biomedical and healthcare applications, Integration, the VLSI Journal, Vol. 71, No. 0, pp. 38 - 48, March, 2020 | BibTex
R. P. Póvoa, R. Arya, A. Canelas, F. Passos, R. M. Martins, N. Lourenço, N. Horta, Sub-μW Tow-Thomas based biquad filter with improved gain for biomedical applications, Microelectronics Journal, Vol. 95, No. 0, pp. 104675 - 104675, January, 2020 | BibTex
R. P. Póvoa, N. Lourenço, R. M. Martins, A. Canelas, N. Horta, JG Goes, A Folded Voltage-Combiners Biased Amplifier for Low Voltage and High Energy-Efficiency Applications, IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 1, No. 1, pp. 1 - 5, April, 2019,
| Abstract | BibTex
A. Canelas, R. P. Póvoa, R. M. Martins, N. Lourenço, J.G. Guilherme, J.P.C Carvalho, N. Horta, FUZYE: A Fuzzy C-Means Analog IC Yield Optimization using Evolutionary-based Algorithms, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. n/a, No. n/a, pp. 1 - 13, November, 2018,
| Abstract | BibTex
F. Passos, R. M. Martins, N. Lourenço, E. Roca, R. P. Póvoa, A. Canelas, R. C.-L. Castro-López, N. Horta, F. V. F, Fernández, Enhanced systematic design of a voltage controlled oscillator using a two-step optimization methodology, Integration, the VLSI Journal, Vol. 63, No. n/a, pp. 351 - 361, September, 2018,
| Abstract | BibTex
J.G. Guilherme, J. Calvillo, R. P. Póvoa, N. Horta, Second-order compensation BGR with low TC and high performance for space applications, Integration, the VLSI Journal, Vol. 1, No. 1, pp. 1 - 10, July, 2018,
| Abstract | BibTex
R. M. Martins, N. Lourenço, F. Passos, R. P. Póvoa, A. Canelas, E. Roca, R. Castro-López, J. S. Sieiro, F. Fernández, N. Horta, Two-Step RF IC Block Synthesis with Pre-Optimized Inductors and Full Layout Generation In-the-loop, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. Early Access, No. Early Access, pp. Early Access - Early Access, May, 2018,
| Abstract | BibTex
R. P. Póvoa, N. Lourenço, R. M. Martins, A. Canelas, N. Horta, JG Goes, Single Stage OTA biased by Voltage-Combiners with Enhanced Performance using Current Starving, IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 1, No. 1, pp. 1 - 5, November, 2017,
| Abstract | BibTex
R. P. Póvoa, N. Lourenço, R. M. Martins, A. Canelas, N. Horta, J. Goes, Single-Stage Amplifier biased by Voltage-Combiners with Gain and Energy-Efficiency Enhancement, IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. PP, No. 99, pp. 1 - 1, March, 2017,
| Abstract | BibTex
N. Lourenço, R. M. Martins, A. Canelas, R. P. Póvoa, N. Horta, AIDA: Layout-aware analog circuit-level sizing with in-loop layout generation, Integration, the VLSI Journal, Vol. 55, No. 09, pp. 316 - 329, September, 2016,
| Abstract | BibTex
M. Pandey, A. Canelas, R. P. Póvoa, J. Torres, J. Costa Freire, N. Lourenço, N. Horta, Design and application of a CMOS active inductor at Ku band based on a multi-objective optimizer, Integration, the VLSI Journal, Vol., No., pp. -, September, 2016 | BibTex
R. M. Martins, R. P. Póvoa, N. Lourenço, N. Horta, Current-flow & Current-Density-aware Multi-Objective Optimization of Analog IC Placement, Integration, the VLSI Journal, Vol. --, No. --, pp. -- - --, June, 2016,
| Abstract | BibTex
R. P. Póvoa, I. Bastos Bastos, N. Lourenço, N. Horta, Automatic Synthesis of RF Front-End Blocks Using Multi-Objective Evolutionary Techniques, Integration, the VLSI Journal, Vol. in press, No. in press, pp. in press - in press, July, 2015,
| Abstract | BibTex
N. Lourenço, A. Canelas, R. P. Póvoa, R. M. Martins, N. Horta, Floorplan-aware analog IC sizing and optimization based on topological constraints, Integration, the VLSI Journal, Vol. 48, No. 1, pp. 183 - 197, January, 2015,
| Abstract | BibTex

31Papers in Conferences

R. Vieira, F. Passos, R. P. Póvoa, R. M. Martins, N. Horta, J.G. Guilherme, N. Lourenço, Architectural Design for Heartbeat Detection Circuits using Verilog-A Behavioral Modeling, IEEE International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD SMACD, Sardinia, Italy, Vol., pp. -, June, 2022,
| Abstract | BibTex
N. Lourenço, F. Passos, R. Vieira, R. M. Martins, N. Horta, J.G. Guilherme, R. P. Póvoa, Radiation-Hardened Bandgap Voltage and Current Reference for Space Applications with 2.38 ppm/ºC Temperature Coefficient, IEEE International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Villasimius, Italy, Vol., pp. -, June, 2022,
| Abstract | Full text (PDF 458 KBs) | BibTex
R. Vieira, F. Passos, A. Canelas, R. P. Póvoa, N. Lourenço, N. Horta, J.G. Guilherme, A Radiation-Hardened Frequency-Locked Loop On-Chip Oscillator with 33.6ppm/ºC Stability for Space Applications, IEEE International Symp. on Circuits and Systems - ISCAS, Austin Texas, United States, May, 2022,
| Abstract | BibTex
R. Vieira, R. M. Martins, N. Horta, N. Lourenço, R. P. Póvoa, A Sub-1µA Low-Power Low-Noise Amplifier with Tunable Gain and Bandwidth for EMG and EOG Biopotential Signals, IEEE PhD. Research in Microelectronics and Electronics - PRIME, Erfurt, Germany, July, 2021,
| Abstract | Full text (PDF 723 KBs) | BibTex
J.G. Guilherme, R. P. Póvoa, N. Lourenço, N. Horta, PROMISE, PROgrammable MIxed Signal ASIC Electronics Framework, ESA International Workshop on Analogue and Mixed-Signal Integrated Circuits for Space Applications AMICSA, Amsterdam, Netherlands, May, 2021,
| Abstract | BibTex
A. Gusmão, N. Lourenço, R. M. Martins, N. Horta, F. Passos, R. P. Póvoa, Semi-Supervised Artificial Neural Networks towards Analog IC Placement Recommender, IEEE International Symposium on Circuits and Systems ISCAS, Sevilla, Spain, October, 2020,
| Abstract | BibTex
N. Lourenço, E. Moutaye, R. M. Martins, A. Canelas, R. P. Póvoa, N. Horta, Hard and Soft Constraints for Multi-objective Analog IC Sizing Optimization, International Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Lausanne, Switzerland, July, 2019,
| Abstract | Full text (PDF 647 KBs) | BibTex
N. Lourenço, E. Afacan, R. M. Martins, F. Passos, A. Canelas, R. P. Póvoa, N. Horta, G. Dundar, Using Polynomial Regression and Artificial Neural Networks for Reusable Analog IC Sizing, International Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Lausanne, Switzerland, July, 2019,
| Abstract | Full text (PDF 908 KBs) | BibTex
R. P. Póvoa, R. M. Martins, N. Lourenço, A. Canelas, N. Horta, JG Goes, A LowNoise CMOS Inverter-Based OTA for Biomedical and Healthcare Signal Receivers, International Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Lausanne, Switzerland, July, 2019 | BibTex
D. Guerra, A. Canelas, R. P. Póvoa, N. Horta, N. Lourenço, R. M. Martins, Artificial Neural Networks as an Alternative for Automatic Analog IC Placement, IEEE International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Lausanne, Switzerland, July, 2019,
| Abstract | BibTex
R. M. Martins, N. Lourenço, R. P. Póvoa, N. Horta, On the Exploration of Design Tradeoffs in Analog IC Placement with Layout-dependent Effects, IEEE International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Lausanne, Switzerland, July, 2019,
| Abstract | BibTex
J.G. Guilherme, J. Z. Zangpo, R. P. Póvoa, N. Horta, An Integrated LC Oscillator with Self Compensation for Frequency Drift and PVT Corners Variations, IEEE International Conf. on Electronics, Circuits and Integrated Systems - ICECS, Bordeaux, France, Vol. 1, pp. 333 - 336, December, 2018,
| Abstract | Full text (PDF 1 MB) | BibTex
N. Lourenço, J. Rosa, R. M. Martins, H. Aidos, A. Canelas, R. P. Póvoa, N. Horta, On the Exploration of Promising Analog IC Designs via Artificial Neural Networks, International Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Prague, Czech Republic, Vol., pp. 133 - 136, July, 2018,
| Abstract | BibTex
J.G. Guilherme, A. Canelas, R. P. Póvoa, N. Lourenço, N. Horta, A 20 dB Gain Two-Stage Low-Noise Amplifier with High Yield for 5 GHz Applications, International Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Prague, Czech Republic, July, 2018,
| Abstract | BibTex
F. Passos, E. Roca, R. Castro-López, F. Fernández, R. P. Póvoa, R. M. Martins, N. Lourenço, A. Canelas, N. Horta, Handling the Effects of Variability and Layout Parasitics in the Automatic Synthesis of LNAs, International Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Prague, Czech Republic, July, 2018 | BibTex
A. Canelas, R. P. Póvoa, R. M. Martins, N. Lourenço, J.G. Guilherme, N. Horta, A 20 DB Gain Two-Stage Low-Noise Amplifier with High Yield for 5 GHz Applications, IEEE International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Prague, Czech Republic, Vol., pp. -, July, 2018,
| Abstract | BibTex
T. Pessoa, N. Lourenço, R. M. Martins, R. P. Póvoa, N. Horta, Enhanced Analog and RF IC Sizing Methodology using PCA and NSGA-II Optimization Kernel, Design, Automation, and Test in Europe - DATE, Dresden, Germany, Vol., pp. 1 - 4, March, 2018,
| Abstract | Full text (PDF 1 MB) | BibTex
R. M. Martins, N. Lourenço, R. P. Póvoa, A. Canelas, N. Horta, F. Passos, R. Castro-López, E. Roca, F. Fernández, Layout-Aware Challenges and a Solution for the Automatic Synthesis of Radio-Frequency IC Blocks, International Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Taormina, Italy, June, 2017,
| Abstract | BibTex
R. P. Póvoa, A. Canelas, R. M. Martins, N. Lourenço, N. Horta, JG Goes, Dynamic Voltage-Combiners Biased OTA for Low-Power High-Speed SC Circuits, IEEE PhD. Research in Microelectronics and Electronics - PRIME, Taormina, Italy, June, 2017 | BibTex
N. Lourenço, R. M. Martins, R. P. Póvoa, A. Canelas, N. Horta, F. Passos, R. Castro-López, E. Roca, F. Fernández, New Mapping Strategies for Pre-Optimized Inductor Sets in Bottom-Up RF IC Sizing Optimization, International Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Taormina, Italy, June, 2017,
| Abstract | BibTex
F. Passos, R. C.-L. Castro-López, E. Roca, F. V. F, Fernández, R. M. Martins, N. Lourenço, R. P. Póvoa, A. Canelas, N. Horta, Systematic Design of a Voltage Controlled Oscillator using a Layout-Aware Approach, International Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Taormina, Italy, June, 2017,
| Abstract | BibTex
A. Canelas, R. M. Martins, R. P. Póvoa, N. Lourenço, N. Horta, Efficient Yield Optimization Method using a Variable K-Means Algorithm for Analog IC Sizing, Design, Automation, and Test in Europe - DATE, Lausanne, Switzerland, Vol. N/A, pp. 1 - 6, March, 2017,
| Abstract | BibTex
A. Canelas, R. M. Martins, R. P. Póvoa, N. Lourenço, N. Horta, Yield Optimization using K-Means Clustering Algorithm to reduce Monte Carlo Simulations, IEEE International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Lisbon, Portugal, Vol. n/a, pp. 1 - 4, June, 2016,
| Abstract | BibTex
R. M. Martins, R. P. Póvoa, N. Lourenço, N. Horta, Exploring Design Tradeoffs in Analog IC Placement with Current-Flow & Current-Density Considerations, International Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Istanbul, Turkey, Vol. n/a, pp. n/a - n/a, September, 2015,
| Abstract | BibTex
R. M. Martins, N. Lourenço, A. Canelas, R. P. Póvoa, N. Horta, AIDA: Robust Layout-Aware Synthesis of Analog ICs including Sizing and Layout Generation, International Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Istanbul, Turkey, Vol. n/a, pp. n/a - n/a, September, 2015,
| Abstract | BibTex
M. Pandey, A. Canelas, R. P. Póvoa, J. Torres, J. Costa Freire, N. Lourenço, N. Horta, Grounded Active Inductors Design Optimization for FQmax = 14.2 GHz using a 130 nm CMOS Technology, International Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Istanbul, Turkey, Vol. -, pp. 1 - 4, September, 2015 | BibTex
R. P. Póvoa, N. Lourenço, N. Horta, J. Goes, A Voltage-Combiners-Biased Amplifier with Enhanced Gain and Speed using Current Starving, IEEE International Symp. on Circuits and Systems - ISCAS, Lisboa, Portugal, May, 2015 | Full text (PDF 418 KBs) | BibTex
R. P. Póvoa, N. Lourenço, N. Horta, RST Santos Tavares, J. Goes, A Cascode-Free Single-Stage Amplifier using a Fully-Differential Folded Voltage-Combiner, IEEE International Conf. on Electronics, Circuits and Systems, Marselha, France, December, 2014 | BibTex
R. P. Póvoa, R. Lourenço Lourenço, N. Lourenço, A. Canelas, R. M. Martins, N. Horta, LC-VCO Automatic Synthesis Using Multi-Objective Evolutionary Techniques, IEEE International Symp. on Circuits and Systems - ISCAS, Melbourne, Australia, June, 2014 | BibTex
R. P. Póvoa, N. Lourenço, N. Horta, RST Santos Tavares, J. Gomes, Single-Stage Amplifiers with Gain Enhancement and Improved Energy-Efficiency employing Voltage-Combiners, IFIP/IEEE International Conf. on Very Large Scale Integration, Istambul, Turkey, October, 2013,
| Abstract | BibTex
F. Rocha, R. P. Póvoa, N. Lourenço, R. M. Martins, N. Horta, A New Metaheuristc Combining Gradient Models with NSGA-II to Enhance Analog IC Synthesis, IEEE Congress on Evolutionary Computation - CEC, Cancún, Mexico, June, 2013 | BibTex

Projects

Closed Projects4

Acronym	Name	Funding Agency	Start date	Ending date
AIDA-C	AIDA-C: Analog IC Optimizer	Thales Alenia Space	01-10-2013	01-11-2021
DISRUPTIVE	DISRUPTIVE - A Paradigm Shift in the Design of Analog and Mixed-Signal Nanoelectronic Circuits and Systems	FCT	01-04-2013	01-12-2016
HAICAS	Hierarchical Analog IC Automatic Synthesis	IT	01-05-2020	30-04-2022
PROMISE	PROgrammable MIxed Signal Electronics	EU/H2020	01-01-2020	31-12-2024

Other Scientific Achievements

6Awards

N. Lourenço, R. M. Martins, A. Canelas, R. P. Póvoa, N. Horta, Best Paper Award 2019 - Integration, the VLSI Journal, N. Lourenço, R. Martins, A. Canelas, R. Póvoa, and N. Horta, “AIDA: Layout-aware Analog Circuit-Level Sizing with In-Loop Layout Generation”, Integration, the VLSI Journal, 2016. DOI: 10.1016/j.vlsi.2016.04.009, 01-07-2019
D. Guerra, N. Lourenço, A. Canelas, R. P. Póvoa, N. Horta, R. M. Martins, Best Paper Award Runner-Up - International Conference on SMACD, Daniel Guerra, António Canelas, Ricardo Póvoa, Nuno Horta, Nuno Lourenço and Ricardo Martins "Artificial Neural Networks as an Alternative for Automatic Analog IC Placement", International Conference on SMACD 2019, Switzerland., 01-07-2019
F. Passos, R. M. Martins, N. Lourenço, E. Roca, R. Castro-López, A. Canelas, R. P. Póvoa, N. Horta, F. V. Fernandez Fernandez, Best Paper Award, Best paper award in SMACD 2018, 01-07-2018
R. M. Martins, N. Lourenço, A. Canelas, R. P. Póvoa, N. Horta, 1st Ranked on “Design Automation Competition” at International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), "AIDA: Robust Layout-Aware Synthesis of Analog ICs including Sizing and Layout Generation" at International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), Istanbul, Turkey., 01-09-2015
R. P. Póvoa, N. Lourenço, N. Horta, JG Goes, Nominee for Best Student Paper Award at IEEE International Symp. on Circuits and Systems (ISCAS), A Voltage-Combiners-Biased Amplifier with Enhanced Gain and Speed using Current Starving, Lisboa, Portugal., 01-05-2015
R. P. Póvoa, R. Lourenço Lourenço, N. Lourenço, A. Canelas, R. M. Martins, N. Horta, Best Student Paper Award Runner-Up at IEEE International Symp. on Circuits and Systems (ISCAS), LC-VCO Automatic Synthesis Using Multi-Objective Evolutionary Techniques, Melbourne, Australia., 01-06-2014

Other Contributions

1Conference Committees

IEEE International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Conference co-chair, 2016

Related UN SDG

Activities from this researcher fall under the following United Nations Strategic Development Goals (SDGs):

IT Member Profile

Ricardo Póvoa

Scientific Achievements

As Co-supervisor

Closed Projects4