Nuno Calado Correia Lourenço

Nuno Lourenço

Former IT academic position:	Assistant Professor
Joining/Leaving IT dates:	09-02-2011 / 30-06-2024
Roles held in IT:	Researcher
Former IT thematic line:	Basic Sciences and Enabling Technologies
Group:	Integrated Circuits - Lx

RESEARCHER ID SCOPUS SCHOLAR

https://www.orcid.org/0000-0002-9625-6435

http://www.cienciavitae.pt/AA17-A737-37DC

By Authors | By Institutions

Scientific Achievements

Degrees

PhD, Instituto Superior Técnico, 12-12-2014
MSc, Instituto Superior Técnico, 28-11-2007
Licenciatura, Instituto Superior Técnico, 01-01-2005

Expertise Topics

Analog IC design automation
Multi -objective evolutionary optimization
Analog IC sizing and Layout Optimization
Deep Learning for Analog IC Design Automation

Affiliations

Instituto Superior Técnico, 01-10-2023, Assistant Professor
IEEE - Institute of Electrical and Electronics Engineers, 01-02-2023, Senior Member
ACM - Association for Computing Machinery, 01-01-2023, Member
IEEE - Institute of Electrical and Electronics Engineers, 01-01-2014 - 01-02-2023, Young Professional

Academic Activities

Supervision of theses

1PhD Student

A Tunable Front-End Receiver IC with High Energy-Efficiency for Biomedical Applications and Healthcare, PhD Student, Rafael Alexandre Ascenso Vieira, Defended 07-2024

5MSc Student

Deep Neural Networks for Behavioral Modeling of Analog ICs, MSc Student, André Carneiro Amaral, Concluded 11-2022
Deep Reinforcement Learning applied to Analog Integrated Circuit Sizing, MSc Student, Tomás Bessa de Curado Rodrigues, Concluded 11-2022
Using Artificial Neural Networks to Size Analog Integrated Circuits, MSc Student, João Pedro da Silva Rosa, Concluded 05-2018
EDA to the cloud –a case study to increase both effectiveness and user experience of EDA tools., MSc Student, Pedro Baptista Sacadura Biscaia, Concluded 05-2018
Enhanced Analog and RF IC Sizing Methodology using PCA and NSGA-II Optimization Kernel, MSc Student, Tiago Claro Oliveira Miranda Pessoa, Concluded 11-2017

Co-Supervision of theses

7MSc Student

Generative Artificial Intelligence for Analog Integrated Circuit Design Automation, MSc Student, Pedro Henrique Menezes Eid, Concluded 11-2024
Semi-Supervised Artificial Neural Networks towards Push-Button Analog IC Placement, MSc Student, António Paiva Lapas de Gusmão, Concluded 11-2019
On the Exploration of Automatic Analog Integrated Circuit Placement using Neural Networks, MSc Student, Daniel José Domingos Guerra, Concluded 10-2018
E-CONF: Sistema de Gestão de Conferências, MSc Student, João Pedro Martins Morais Luís, Concluded 11-2016
AIDA-C: Evolutionary Optimization Techniques applied to Analog IC Design, MSc Student, André Ferreira, Concluded 06-2016
AIDA-C: Cluster Computing applied to Circuit Level Synthesis and Simulation, MSc Student, David Neves, Concluded 10-2015
AIDA-X: Aplicação de Software para Extracção de Netlists de Layouts de Circuitos Interados Analógicos, MSc Student, Bruno Cardoso, Concluded 05-2015

Publications

10Books

P. E. Eid, F. A. Azevedo, N. Lourenço, R. M. Martins, Efficient Analog Integrated Circuit Sizing with GenAI: Exploring Generative Diffusion Models, Springer, Cham, Cham, 2025,
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J. Domingues, P. Vaz, A. Gusmão, N. Horta, N. Lourenço, R. M. Martins, Speeding-Up Radio-Frequency Integrated Circuit Sizing with Neural Networks, Springer, Cham, Cham, 2023,
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R. Vieira, R. P. Póvoa, N. Lourenço, N. Horta, Tunable Low-Power Low-Noise Amplifier For Healthcare Applications, Springer International Publishing, Lisboa, 2021,
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A. Gusmão, N. Horta, N. Lourenço, R. M. Martins, Analog IC Placement Generation via Neural Networks from Unlabeled Data, Springer International Publishing, Lisbon, 2020,
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J. Rosa, D. Guerra, N. Horta, R. M. Martins, N. Lourenço, Using Artificial Neural Networks for Analog Integrated Circuit Design Automation, Springer, Gewerbestrasse 11, 6330 Cham, Switzerland, 2020,
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N. Lourenço, R. M. Martins, N. Horta, Automatic Analog IC Sizing and Optimization Constrained with PVT Corners and Layout Effects, Springer International Publishing, Switzerland, 2017,
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R. M. Martins, N. Lourenço, N. Horta, Analog Integrated Circuit Design Automation – Placement, Routing and Parasitic Extraction Techniques, Springer International Publishing, Switzerland, 2017,
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R. Lourenço Lourenço, N. Lourenço, N. Horta, AIDA-CMK: Multi-Algorithm Optimization Kernel applied to Analog IC Sizing, Springer, Heidelberg, New York, London, 2015,
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F. Rocha, R. M. Martins, N. Lourenço, N. Horta, Electronic Design Automation of Analog ICs combining Gradient Models with Multi-Objective Evolutionary Algorithms, Springer, Heidelberg, 2014,
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R. M. Martins, N. Lourenço, N. Horta, Generating Analog IC Layouts with LAYGEN II, Springer, n/a, 2013,
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3Books Chapters

A. Canelas, R. M. Martins, R. P. Póvoa, N. Lourenço, J.G. Guilherme, N. Horta, Enhancing an Automatic Analog IC Design Flow by using a Technology-Independent Module Generator, Chapter in, Performance Optimization Techniques in Analog, Mixed-Signal, and Radio-Frequency Circuit Design, Mourad Fakhfakh, Esteban Tlelo-Cuautle, Maria Helena Fino, IGI global, Medical Information Science Reference, 2014
R. P. Póvoa, N. Lourenço, A. Canelas, R. M. Martins, N. Horta, Synthesis of LC-Oscillators using Rival Multi-Objective/Multi-Constraint Optimization Kernels, Chapter in, Performance Optimization Techniques in Analog, Mixed-Signal, and Radio-Frequency Circuit Design, Mourad Fakhfakh, Esteban Tlelo-Cuautle, Maria Helena Fino, IGI global, Medical Information Science Reference, 2014
N. Lourenço, R. M. Martins, M.B. Barros, N. Horta, Analog Circuit Design based on Robust POFs using an Enhanced MOEA with SVM Models, Chapter in, Analog/RF and Mixed-Signal Circuit Systematic Design, Mourad Fakhfakh, Esteban Tlelo-Cuautle, Rafael Castro-Lopez, Springer, Heidelberg, 2013

37Papers in Journals

F. A. Azevedo, N. Lourenço, R. M. Martins, Comprehensive application of denoising diffusion probabilistic models towards the automation of analog integrated circuit sizing, Expert Systems with Applications, Vol. 290, No., pp. 128414 - 128414, September, 2025,
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P. E. Eid, F. A. Azevedo, N. Lourenço, R. M. Martins, Using Denoising Diffusion Probabilistic Models to solve the inverse sizing problem of analog Integrated Circuits, AEU - International Journal of Electronics and Communications, Vol. 195, No., pp. 155767 - 155767, May, 2025,
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L. Mendes, J. C. Silva Silva, N. Lourenço, J. Vaz, R. M. Martins, F. Passos, Fully Automatically Synthesized mm-Wave Low-Noise Amplifiers for 5G/6G Applications, IEEE Transactions on Microwave Theory and Techniques, Vol. 73, No. 8, pp. 4828 - 4841, February, 2025,
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P. M. Santos, R. Lameirinhas, C. P. C. V. B. P. Correia V. Bernardo, J. Torres, A. Serralheiro, R. Vieira, N. Lourenço, Fully CMOS Boost Converter Operating at 2.65 GHz for Photovoltaic Energy Harvesting, IEEE Access, Vol. 13, No., pp. 19365 - 19378, January, 2025,
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R. Vieira, F. Naf, R. M. Martins, N. Horta, N. Lourenço, R. P. Póvoa, A Tunable Gain and Bandwidth Low-Noise Amplifier with 1.44 NEF for EMG and EOG Biopotential Signal, Electronics, Vol. 12, No. 2592, pp. 1 - 17, June, 2023,
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F. Passos, N. Lourenço, E. Roca, R. M. Martins, R. Castro-López, N. Horta, F. Fernández, PACOSYT: A Passive Component Synthesis Tool Based on Machine Learning and Tailored Modeling Strategies Towards Optimal RF and mm-Wave Circuit Designs, IEEE Journal of Microwaves, Vol. 3, No. 2, pp. 599 - 613, April, 2023,
| Abstract | Full text (PDF 4 MBs) | BibTex
R. M. Martins, N. Lourenço, Analog Integrated Circuit Routing Techniques: An Extensive Review, IEEE Access, Vol. 11, No. 0, pp. 35965 - 35983, April, 2023,
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R. Vieira, F. Passos, R. M. Martins, N. Horta, N. Lourenço, Behavioral Analysis of Noise and Bandwidth Specifications of Heartbeat Detection Circuits for Ultra Low Power Devices, IEEE Access, Vol. 11, No. 0, pp. 27330 - 27341, March, 2023,
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A. Gusmão, Alves P. Alves, N. Horta, N. Lourenço, R. M. Martins, Differentiable Constraints’ Encoding for Gradient-Based Analog Integrated Circuit Placement Optimization, Electronics, Vol. 12, No. 1, pp. 110 - 110, December, 2022 | BibTex
A. Gusmão, N. Horta, N. Lourenço, R. M. Martins, Scalable and order invariant analog integrated circuit placement with Attention-based Graph-to-Sequence deep models, Expert Systems with Applications, Vol. 207, No. 1, pp. 117954 - 117954, November, 2022 | Full text (PDF 4 MBs) | BibTex
A. Gusmão, R. Vieira, N. Horta, N. Lourenço, R. M. Martins, Exploiting a Deep Learning Toolbox for Human-Machine Feedback towards Analog Integrated Circuit Placement Automation, Electronics, Vol. 11, No. 23, pp. 1 - 1, November, 2022,
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A. Gusmão, R. P. Póvoa, N. Horta, N. Lourenço, R. M. Martins, DeepPlacer: A custom integrated OpAmp placement tool using deep models, Applied Soft Computing Journal, Vol. 115, No. 1, pp. 108188 - 108188, January, 2022,
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A. Canelas, F. Passos, N. Lourenço, R. M. Martins, E. Roca, R. Castro-López, N. Horta, F. V. Fernandez Fernandez, Hierarchical Yield-Aware Synthesis Methodology Covering Device-, Circuit-, and System-Level for Radiofrequency ICs, IEEE Access, Vol. 9, No. 1, pp. 124152 - 124164, September, 2021,
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L. Mendes, J. Vaz, F. Passos, N. Lourenço, R. M. Martins, In-Depth Design Space Exploration of 26.5-to-29.5-GHz 65-nm CMOS Low-Noise Amplifiers for Low-Footprint-and-Power 5G Communications Using One-and- Two -Step Design Optimization, IEEE Access, Vol. 9, No. --, pp. 70353 - 70368, May, 2021,
| Abstract | Full text (PDF 3 MBs) | BibTex
R. M. Martins, N. Lourenço, R. P. Póvoa, N. Horta, Shortening the gap between pre- and post-layout analog IC performance by reducing the LDE-induced variations with multi-objective simulated quantum annealing, Engineering Applications of Artificial Intelligence, Vol. 98, No. n/a, pp. 104102 - 104102, February, 2021,
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R. M. Martins, N. Lourenço, N. Horta, J. Y. Yin, P. M. Mak, R. P. M. Martins, Design of a 4.2-to-5.1 GHz Ultralow-Power Complementary Class-B/C Hybrid-Mode VCO in 65-nm CMOS Fully Supported by EDA Tools, IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 67, No. 11, pp. 3965 - 3977, November, 2020,
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E. Afacan, N. Lourenço, R. M. Martins, G. Dundar, Review: Machine learning techniques in analog/RF integrated circuit design, synthesis, layout, and test, Integration, the VLSI Journal, Vol. -, No. -, pp. - - -, November, 2020,
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R. P. Póvoa, A. Canelas, R. M. Martins, N. Lourenço, N. Horta, JG Goes, A new family of CMOS inverter-based OTAs for biomedical and healthcare applications, Integration, the VLSI Journal, Vol. 71, No. 0, pp. 38 - 48, March, 2020 | BibTex
F. Passos, E. Roca, R. M. Martins, N. Lourenço, S. Ahyoune Ahyoune, J. S. Sieiro, R. Castro-López, N. Horta, F. V. Fernandez Fernandez, Ready-to-Fabricate RF Circuit Synthesis Using a Layout- and Variability-Aware Optimization-Based Methodology, IEEE Access, Vol. 8, No. -, pp. 51601 - 51609, March, 2020 | BibTex
R. P. Póvoa, R. Arya, A. Canelas, F. Passos, R. M. Martins, N. Lourenço, N. Horta, Sub-μW Tow-Thomas based biquad filter with improved gain for biomedical applications, Microelectronics Journal, Vol. 95, No. 0, pp. 104675 - 104675, January, 2020 | BibTex
R. P. Póvoa, N. Lourenço, R. M. Martins, A. Canelas, N. Horta, JG Goes, A Folded Voltage-Combiners Biased Amplifier for Low Voltage and High Energy-Efficiency Applications, IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 1, No. 1, pp. 1 - 5, April, 2019,
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R. M. Martins, N. Lourenço, N. Horta, J. Y. Yin, P. M. Mak, R. P. M. Martins, Many-Objective Sizing Optimization of a Class-C/D VCO for Ultralow-Power IoT and Ultralow- Phase-Noise Cellular Applications, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 27, No. 1, pp. 69 - 82, January, 2019,
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A. Canelas, R. P. Póvoa, R. M. Martins, N. Lourenço, J.G. Guilherme, J.P.C Carvalho, N. Horta, FUZYE: A Fuzzy C-Means Analog IC Yield Optimization using Evolutionary-based Algorithms, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. n/a, No. n/a, pp. 1 - 13, November, 2018,
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F. Passos, R. M. Martins, N. Lourenço, E. Roca, R. P. Póvoa, A. Canelas, R. C.-L. Castro-López, N. Horta, F. V. F, Fernández, Enhanced systematic design of a voltage controlled oscillator using a two-step optimization methodology, Integration, the VLSI Journal, Vol. 63, No. n/a, pp. 351 - 361, September, 2018,
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R. M. Martins, N. Lourenço, F. Passos, R. P. Póvoa, A. Canelas, E. Roca, R. Castro-López, J. S. Sieiro, F. Fernández, N. Horta, Two-Step RF IC Block Synthesis with Pre-Optimized Inductors and Full Layout Generation In-the-loop, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. Early Access, No. Early Access, pp. Early Access - Early Access, May, 2018,
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R. P. Póvoa, N. Lourenço, R. M. Martins, A. Canelas, N. Horta, JG Goes, Single Stage OTA biased by Voltage-Combiners with Enhanced Performance using Current Starving, IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 1, No. 1, pp. 1 - 5, November, 2017,
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R. M. Martins, N. Lourenço, A. Canelas, N. Horta, Stochastic-based placement template generator for analog IC layout-aware synthesis, Integration, the VLSI Journal, Vol. 58, No. n/a, pp. 485 - 495, June, 2017,
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R. P. Póvoa, N. Lourenço, R. M. Martins, A. Canelas, N. Horta, J. Goes, Single-Stage Amplifier biased by Voltage-Combiners with Gain and Energy-Efficiency Enhancement, IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. PP, No. 99, pp. 1 - 1, March, 2017,
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N. Lourenço, R. M. Martins, A. Canelas, R. P. Póvoa, N. Horta, AIDA: Layout-aware analog circuit-level sizing with in-loop layout generation, Integration, the VLSI Journal, Vol. 55, No. 09, pp. 316 - 329, September, 2016,
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M. Pandey, A. Canelas, R. P. Póvoa, J. Torres, J. Costa Freire, N. Lourenço, N. Horta, Design and application of a CMOS active inductor at Ku band based on a multi-objective optimizer, Integration, the VLSI Journal, Vol., No., pp. -, September, 2016 | BibTex
R. M. Martins, R. P. Póvoa, N. Lourenço, N. Horta, Current-flow & Current-Density-aware Multi-Objective Optimization of Analog IC Placement, Integration, the VLSI Journal, Vol. --, No. --, pp. -- - --, June, 2016,
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R. M. Martins, N. Lourenço, N. Horta, Multi-objective optimization of analog integrated circuit placement hierarchy in absolute coordinates, Expert Systems with Applications, Vol. 42, No. 23, pp. 9137 - 9151, December, 2015,
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R. P. Póvoa, I. Bastos Bastos, N. Lourenço, N. Horta, Automatic Synthesis of RF Front-End Blocks Using Multi-Objective Evolutionary Techniques, Integration, the VLSI Journal, Vol. in press, No. in press, pp. in press - in press, July, 2015,
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N. Lourenço, A. Canelas, R. P. Póvoa, R. M. Martins, N. Horta, Floorplan-aware analog IC sizing and optimization based on topological constraints, Integration, the VLSI Journal, Vol. 48, No. 1, pp. 183 - 197, January, 2015,
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R. M. Martins, N. Lourenço, A. Canelas, N. Horta, Electromigration-aware analog Router with multilayer multiport terminal structures, Integration, the VLSI Journal, Vol. 47, No. 4, pp. 532 - 547, September, 2014,
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R. M. Martins, N. Lourenço, N. Horta, LAYGEN II—Automatic Layout Generation of Analog Integrated Circuits, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 32, No. 11, pp. 1641 - 1654, November, 2013,
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R. M. Martins, N. Lourenço, A. Canelas, N. Horta, Routing analog ICs using a multi-objective multi-constraint evolutionary approach, Analog Integrated Circuits and Signal Processing, Vol. 78, No. 1, pp. 123 - 135, June, 2013,
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74Papers in Conferences

F. A. Azevedo, N. Lourenço, R. M. Martins, Late Breaking Results: Encoder-Decoder Generative Diffusion Transformer Towards Push-Button Analog IC Sizing, ACM/IEEE Design Automation Conference (DAC), San Francisco, United States, Vol., pp. -, June, 2025,
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R. M. Martins, N. Lourenço, An Efficient Performance-driven Analog IC Placement Optimizer via Extremely Randomized Tree-based Post-Layout Performance Regressors, IFIP/IEEE International Conference on Very Large Scale Integration VLSI-SoC, Tangier, Morocco, Vol., pp. -, October, 2024,
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R. M. Martins, A. Gusmão, R. Vieira, F. Passos, N. Lourenço, N. Horta, PONDEROUS: A Performance-driven Analog IC Placement Optimizer Leveraged by a ML Pipeline, IEEE International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Volos, Greece, Vol., pp. -, July, 2024,
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R. Vieira, S. H. Hatefinasab, R. M. Martins, N. Horta, N. Lourenço, A 25 nW Heartbeat Monitoring Circuit for Wearable Applications in CMOS 65nm, IEEE International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Vólos, Greece, July, 2024,
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P. E, Eid, F. A. Azevedo, R. M. Martins, N. Lourenço, Solving the Inverse Problem of Analog Integrated Circuit Sizing with Diffusion Models, IEEE International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Volos, Greece, Vol., pp. -, July, 2024,
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D. P. Peneda, F. A. Azevedo, N. Lourenço, N. Horta, R. M. Martins, Effective Routing Probability Maps via Convolutional Neural Networks for Analog IC Layout Automation, International Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Volos, Greece, Vol., pp. -, July, 2024,
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F. Passos, R. M. Martins, N. Lourenço, Low-Power 9.6-11GHz and 10.8-12GHz VCOs Designed for a 2.5/5GHz TRx using High-Q Inductors Synthesized with ML Techniques, IEEE International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Volos, Greece, Vol., pp. -, July, 2024 | BibTex
A. Amaral, A. Gusmão, R. Vieira, R. M. Martins, N. Horta, N. Lourenço, An ANN-Based Approach to the Modeling and Simulation of Analog Circuits, IEEE International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD SMACD, Funchal, Portugal, Vol., pp. -, July, 2023,
| Abstract | BibTex
R. Vieira, R. M. Martins, N. Horta, N. Lourenço, Design Space Exploration of Single-Stage OTAs towards an Ultra-Low-Power LNA for ECG Signals, IEEE International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Funchal, Portugal, July, 2023,
| Abstract | BibTex
F. Passos, N. Lourenço, L. Mendes, R. M. Martins, J. Vaz, N. Horta, A 23.5–32.5GHz, 17dBm PSAT and 37.5% PAE Power Amplifier Synthesized Using an Automated Design Methodology, IEEE International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Funchal, Portugal, July, 2023 | BibTex
F. Passos, N. Lourenço, L. Mendes, R. M. Martins, J. Vaz, N. Horta, A 23.5-32.5GHz, 17dBm PSAT and 37.5% PAE Power Amplifier Synthesized Using an Automated Design Methodology, IEEE International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Funchal, Portugal, Vol., pp. -, July, 2023 | BibTex
F. Passos, R. M. Martins, N. Lourenço, L. Mendes, J. Vaz, N. Horta, Efficient Hierarchical mm-Wave System Synthesis with Embedded Accurate Transformer and Balun Machine Learning Models, Asia and South Pacific Design Automation Conference ASP-DAC, Tokyo, Japan, January, 2023,
| Abstract | BibTex
F. Passos, R. M. Martins, N. Lourenço, L. Mendes, J. Vaz, N. Horta, Efficient Hierarchical mm-Wave System Synthesis with Embedded Accurate Transformer and Balun Machine Learning Models, Asia and South Pacific Design Automation Conference ASP-DAC, Tokyo, Japan, Vol., pp. 64 - 69, January, 2023 | BibTex
J. Domingues, A. Gusmão, N. Horta, N. Lourenço, R. M. Martins, Accelerating Voltage-Controlled Oscillator Sizing Optimizations with ANN-based Convergence Classifiers and Frequency Guess Predictors, IEEE International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Sardinia, Italy, Vol., pp. -, June, 2022,
| Abstract | Full text (PDF 784 KBs) | BibTex
F. Passos, N. Lourenço, R. M. Martins, E. Roca, R. Castro-López, N. Horta, F. V. Fernandez Fernandez, Machine Learning Approaches for Transformer Modeling, IEEE International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Villasimius, Italy, June, 2022 | BibTex
R. Vieira, F. Passos, R. P. Póvoa, R. M. Martins, N. Horta, J.G. Guilherme, N. Lourenço, Architectural Design for Heartbeat Detection Circuits using Verilog-A Behavioral Modeling, IEEE International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD SMACD, Sardinia, Italy, Vol., pp. -, June, 2022,
| Abstract | BibTex
Alves P. Alves, A. Gusmão, N. Horta, N. Lourenço, R. M. Martins, ANN-based Analog IC Floorplan Recommender with a Broader Topological Constraints Coverage, IEEE International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Sardinia, Italy, Vol., pp. -, June, 2022,
| Abstract | Full text (PDF 898 KBs) | BibTex
N. Lourenço, F. Passos, R. Vieira, R. M. Martins, N. Horta, J.G. Guilherme, R. P. Póvoa, Radiation-Hardened Bandgap Voltage and Current Reference for Space Applications with 2.38 ppm/ºC Temperature Coefficient, IEEE International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Villasimius, Italy, Vol., pp. -, June, 2022,
| Abstract | Full text (PDF 458 KBs) | BibTex
R. Vieira, F. Passos, A. Canelas, R. P. Póvoa, N. Lourenço, N. Horta, J.G. Guilherme, A Radiation-Hardened Frequency-Locked Loop On-Chip Oscillator with 33.6ppm/ºC Stability for Space Applications, IEEE International Symp. on Circuits and Systems - ISCAS, Austin Texas, United States, May, 2022,
| Abstract | BibTex
L. Mendes, J. Vaz, F. Passos, N. Lourenço, R. M. Martins, Automatic Design of High-Gain 26.5-to-29.5-GHz Transformer-Less Low-Noise Amplifier 1.86-to-8.87-mW Variants in 65-nm CMOS, IEEE International Symposium on Circuits and Systems ISCAS, Austin, United States, May, 2022,
| Abstract | BibTex
A. Gusmão, N. Horta, N. Lourenço, R. M. Martins, Late Breaking Results: Attention in Graph2Seq Neural Networks towards Push-Button Analog IC Placement, ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, United States, December, 2021,
| Abstract | BibTex
R. Vieira, R. M. Martins, N. Horta, N. Lourenço, R. P. Póvoa, A Sub-1µA Low-Power Low-Noise Amplifier with Tunable Gain and Bandwidth for EMG and EOG Biopotential Signals, IEEE PhD. Research in Microelectronics and Electronics - PRIME, Erfurt, Germany, July, 2021,
| Abstract | Full text (PDF 723 KBs) | BibTex
R. M. Martins, A. Gusmão, A. Canelas, F. Passos, N. Lourenço, N. Horta, An Essay on the Next Generation of Performance-driven Analog/RF IC EDA Tools: The Role of Simulation-based Layout Optimization, IEEE International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Erfurt, Germany, July, 2021,
| Abstract | BibTex
A. Gusmão, A. Canelas, N. Horta, N. Lourenço, R. M. Martins, A Deep Learning Toolbox for Analog Integrated Circuit Placement, IEEE International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Conference online, July, 2021,
| Abstract | BibTex
A. Gusmão, N. Lourenço, R. M. Martins, N. Horta, Bringing Structure into Analog IC Placement with Relational Graph Convolutional Networks, IEEE International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Conference online, July, 2021,
| Abstract | BibTex
J.G. Guilherme, R. P. Póvoa, N. Lourenço, N. Horta, PROMISE, PROgrammable MIxed Signal ASIC Electronics Framework, ESA International Workshop on Analogue and Mixed-Signal Integrated Circuits for Space Applications AMICSA, Amsterdam, Netherlands, May, 2021,
| Abstract | BibTex
A. Gusmão, N. Lourenço, R. M. Martins, N. Horta, F. Passos, R. P. Póvoa, Semi-Supervised Artificial Neural Networks towards Analog IC Placement Recommender, IEEE International Symposium on Circuits and Systems ISCAS, Sevilla, Spain, October, 2020,
| Abstract | BibTex
N. Lourenço, E. Moutaye, R. M. Martins, A. Canelas, R. P. Póvoa, N. Horta, Hard and Soft Constraints for Multi-objective Analog IC Sizing Optimization, International Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Lausanne, Switzerland, July, 2019,
| Abstract | Full text (PDF 647 KBs) | BibTex
N. Lourenço, E. Afacan, R. M. Martins, F. Passos, A. Canelas, R. P. Póvoa, N. Horta, G. Dundar, Using Polynomial Regression and Artificial Neural Networks for Reusable Analog IC Sizing, International Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Lausanne, Switzerland, July, 2019,
| Abstract | Full text (PDF 908 KBs) | BibTex
R. P. Póvoa, R. M. Martins, N. Lourenço, A. Canelas, N. Horta, JG Goes, A LowNoise CMOS Inverter-Based OTA for Biomedical and Healthcare Signal Receivers, International Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Lausanne, Switzerland, July, 2019 | BibTex
D. Guerra, A. Canelas, R. P. Póvoa, N. Horta, N. Lourenço, R. M. Martins, Artificial Neural Networks as an Alternative for Automatic Analog IC Placement, IEEE International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Lausanne, Switzerland, July, 2019,
| Abstract | BibTex
R. M. Martins, N. Lourenço, R. P. Póvoa, N. Horta, On the Exploration of Design Tradeoffs in Analog IC Placement with Layout-dependent Effects, IEEE International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Lausanne, Switzerland, July, 2019,
| Abstract | BibTex
R. M. Martins, N. Lourenço, N. Horta, J. Y. Yin, P. M. Mak, R. P. M. Martins, Using EDA Tools to Push the Performance Boundaries of an Ultralow-Power IoT-VCO at 65nm, IEEE International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Lausanne, Switzerland, July, 2019,
| Abstract | BibTex
N. Lourenço, J. Rosa, R. M. Martins, H. Aidos, A. Canelas, R. P. Póvoa, N. Horta, On the Exploration of Promising Analog IC Designs via Artificial Neural Networks, International Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Prague, Czech Republic, Vol., pp. 133 - 136, July, 2018,
| Abstract | BibTex
J.G. Guilherme, A. Canelas, R. P. Póvoa, N. Lourenço, N. Horta, A 20 dB Gain Two-Stage Low-Noise Amplifier with High Yield for 5 GHz Applications, International Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Prague, Czech Republic, July, 2018,
| Abstract | BibTex
F. Passos, E. Roca, R. Castro-López, F. Fernández, R. P. Póvoa, R. M. Martins, N. Lourenço, A. Canelas, N. Horta, Handling the Effects of Variability and Layout Parasitics in the Automatic Synthesis of LNAs, International Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Prague, Czech Republic, July, 2018 | BibTex
R. M. Martins, N. Lourenço, N. Horta, J. Y. Yin, P. M. Mak, R. P. M. Martins, Design and Optimization of a Class-C/D VCO for Ultra-Low-Power IoT and Cellular Applications, IEEE International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Prague, Czech Republic, July, 2018,
| Abstract | BibTex
A. Canelas, R. P. Póvoa, R. M. Martins, N. Lourenço, J.G. Guilherme, N. Horta, A 20 DB Gain Two-Stage Low-Noise Amplifier with High Yield for 5 GHz Applications, IEEE International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Prague, Czech Republic, Vol., pp. -, July, 2018,
| Abstract | BibTex
T. Pessoa, N. Lourenço, R. M. Martins, R. P. Póvoa, N. Horta, Enhanced Analog and RF IC Sizing Methodology using PCA and NSGA-II Optimization Kernel, Design, Automation, and Test in Europe - DATE, Dresden, Germany, Vol., pp. 1 - 4, March, 2018,
| Abstract | Full text (PDF 1 MB) | BibTex
R. M. Martins, N. Lourenço, R. P. Póvoa, A. Canelas, N. Horta, F. Passos, R. Castro-López, E. Roca, F. Fernández, Layout-Aware Challenges and a Solution for the Automatic Synthesis of Radio-Frequency IC Blocks, International Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Taormina, Italy, June, 2017,
| Abstract | BibTex
R. P. Póvoa, A. Canelas, R. M. Martins, N. Lourenço, N. Horta, JG Goes, Dynamic Voltage-Combiners Biased OTA for Low-Power High-Speed SC Circuits, IEEE PhD. Research in Microelectronics and Electronics - PRIME, Taormina, Italy, June, 2017 | BibTex
N. Lourenço, R. M. Martins, R. P. Póvoa, A. Canelas, N. Horta, F. Passos, R. Castro-López, E. Roca, F. Fernández, New Mapping Strategies for Pre-Optimized Inductor Sets in Bottom-Up RF IC Sizing Optimization, International Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Taormina, Italy, June, 2017,
| Abstract | BibTex
F. Passos, R. C.-L. Castro-López, E. Roca, F. V. F, Fernández, R. M. Martins, N. Lourenço, R. P. Póvoa, A. Canelas, N. Horta, Systematic Design of a Voltage Controlled Oscillator using a Layout-Aware Approach, International Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Taormina, Italy, June, 2017,
| Abstract | BibTex
A. Canelas, R. M. Martins, R. P. Póvoa, N. Lourenço, N. Horta, Efficient Yield Optimization Method using a Variable K-Means Algorithm for Analog IC Sizing, Design, Automation, and Test in Europe - DATE, Lausanne, Switzerland, Vol. N/A, pp. 1 - 6, March, 2017,
| Abstract | BibTex
J. Cachaço, N. Machado, N. Lourenço, J.G. Guilherme, N. Horta, Automatic Technology Migration of Analog IC Designs using Generic Cell Libraries, Design, Automation, and Test in Europe - DATE, Lausanne, Switzerland, Vol. N/A, pp. 1 - 4, March, 2017,
| Abstract | BibTex
A. Ferreira, N. Lourenço, R. M. Martins, N. Horta, Automated analog IC design constraints generation for a layout-aware sizing approach, IEEE International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Lisboa, Portugal, Vol. --, pp. 1 - 4, June, 2016,
| Abstract | BibTex
A. Canelas, R. M. Martins, R. P. Póvoa, N. Lourenço, N. Horta, Yield Optimization using K-Means Clustering Algorithm to reduce Monte Carlo Simulations, IEEE International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Lisbon, Portugal, Vol. n/a, pp. 1 - 4, June, 2016,
| Abstract | BibTex
R. M. Martins, A. Canelas, N. Lourenço, N. Horta, On-the-fly Exploration of Placement Templates for Analog IC Layout-aware Sizing Methodologies, IEEE International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Lisboa, Portugal, Vol. n/a, pp. 1 - 4, June, 2016 | BibTex
D. Neves, R. M. Martins, N. Lourenço, N. Horta, Design Automation Tasks Scheduling for Enhanced Parallel Execution of a State-of-the-Art Layout-Aware Sizing Approach, Design, Automation, and Test in Europe - DATE, Dresden, Germany, Vol. n/a, pp. 1 - 4, March, 2016,
| Abstract | BibTex
R. M. Martins, N. Lourenço, N. Horta, M. Santos, Embedding Fault List Compression Techniques in a Design Automation Framework for Analog and Mixed-Signal Structural Testing, Conference on Design of Circuits and Integrated Systems DCIS, Estoril, Portugal, Vol. n/a, pp. n/a - n/a, November, 2015,
| Abstract | BibTex
R. M. Martins, R. P. Póvoa, N. Lourenço, N. Horta, Exploring Design Tradeoffs in Analog IC Placement with Current-Flow & Current-Density Considerations, International Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Istanbul, Turkey, Vol. n/a, pp. n/a - n/a, September, 2015,
| Abstract | BibTex
R. M. Martins, N. Lourenço, A. Canelas, R. P. Póvoa, N. Horta, AIDA: Robust Layout-Aware Synthesis of Analog ICs including Sizing and Layout Generation, International Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Istanbul, Turkey, Vol. n/a, pp. n/a - n/a, September, 2015,
| Abstract | BibTex
D. Neves, N. Lourenço, N. Horta, Scheduling evaluation tasks for increased efficiency of parallel analog IC synthesis, International Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Istanbul, Turkey, Vol. na, pp. 1 - 4, September, 2015,
| Abstract | BibTex
M. Pandey, A. Canelas, R. P. Póvoa, J. Torres, J. Costa Freire, N. Lourenço, N. Horta, Grounded Active Inductors Design Optimization for FQmax = 14.2 GHz using a 130 nm CMOS Technology, International Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Istanbul, Turkey, Vol. -, pp. 1 - 4, September, 2015 | BibTex
R. M. Martins, N. Lourenço, N. Horta, Analog IC Placement using Absolute Coordinates and a Hierarchical Combination of Pareto Optimal Fronts, IEEE PhD. Research in Microelectronics and Electronics - PRIME, Glasgow, United Kingdom, June, 2015,
| Abstract | BibTex
B. Cardoso, R. M. Martins, N. Lourenço, N. Horta, AIDA-PEx: Accurate Parasitic Extraction for Layout-Aware Analog Integrated Circuit Sizing, IEEE PhD. Research in Microelectronics and Electronics - PRIME, Glasgow, United Kingdom, June, 2015,
| Abstract | BibTex
R. P. Póvoa, N. Lourenço, N. Horta, J. Goes, A Voltage-Combiners-Biased Amplifier with Enhanced Gain and Speed using Current Starving, IEEE International Symp. on Circuits and Systems - ISCAS, Lisboa, Portugal, May, 2015 | Full text (PDF 418 KBs) | BibTex
R. M. Martins, N. Lourenço, A. Canelas, N. Horta, Extraction and Application of Wiring Symmetry Rules to Route Analog Multiport Terminals, IEEE International Symp. on Circuits and Systems - ISCAS, Lisboa, Portugal, Vol. n/a, pp. 1945 - 1948, May, 2015,
| Abstract | BibTex
N. Lourenço, R. M. Martins, N. Horta, Layout-Aware Sizing of Analog ICs using Floorplan & Routing Estimates for Parasitic Extraction, Design, Automation and Test in Europe Conf., Grenoble, France, Vol. 0, pp. 1 - 6, March, 2015,
| Abstract | BibTex
R. P. Póvoa, N. Lourenço, N. Horta, RST Santos Tavares, J. Goes, A Cascode-Free Single-Stage Amplifier using a Fully-Differential Folded Voltage-Combiner, IEEE International Conf. on Electronics, Circuits and Systems, Marselha, France, December, 2014 | BibTex
R. P. Póvoa, R. Lourenço Lourenço, N. Lourenço, A. Canelas, R. M. Martins, N. Horta, LC-VCO Automatic Synthesis Using Multi-Objective Evolutionary Techniques, IEEE International Symp. on Circuits and Systems - ISCAS, Melbourne, Australia, June, 2014 | BibTex
R. M. Martins, N. Lourenço, A. Canelas, N. Horta, Electromigration-Aware and IR-Drop Avoidance Routing in Analog Multiport Terminal Structures, Design, Automation, and Test in Europe - DATE, Dresden, Germany, Vol. n/a, pp. 1 - 6, March, 2014,
| Abstract | BibTex
R. P. Póvoa, N. Lourenço, N. Horta, RST Santos Tavares, J. Gomes, Single-Stage Amplifiers with Gain Enhancement and Improved Energy-Efficiency employing Voltage-Combiners, IFIP/IEEE International Conf. on Very Large Scale Integration, Istambul, Turkey, October, 2013,
| Abstract | BibTex
F.C. Cadete, N. Lourenço, M.B. Barros, R. M. Martins, N. Horta, A New Metaheuristc Combining Gradient Models with NSGA-II to Enhance Analog IC Synthesis, IEEE Congress on Evolutionary Computation - CEC, Cancun, Mexico, June, 2013,
| Abstract | BibTex
R. M. Martins, N. Lourenço, A. Canelas, N. Horta, Multi-Port Multi-Terminal Analog Router based on an Evolutionary Optimization Kernel, IEEE Congress on Evolutionary Computation - CEC, Cancún, Mexico, Vol. n/a, pp. 2789 - 2796, June, 2013,
| Abstract | BibTex
F. Rocha, R. P. Póvoa, N. Lourenço, R. M. Martins, N. Horta, A New Metaheuristc Combining Gradient Models with NSGA-II to Enhance Analog IC Synthesis, IEEE Congress on Evolutionary Computation - CEC, Cancún, Mexico, June, 2013 | BibTex
F.C. Cadete, R. M. Martins, N. Lourenço, N. Horta, Enhancing a Layout-Aware Synthesis Methodology for Analog ICs by Embedding Statistical Knowledge into the Evolutionary Optimization Kernel, Doctoral Conf. on Computing, Electrical and Industrial Systems - DOCEIS, Lisbon, Portugal, April, 2013,
| Abstract | BibTex
R. M. Martins, N. Lourenço, N. Horta, Multi-Objective Multi-Constraint Routing of Analog ICs using a Modified NSGA-II Approach, International Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Seville, Spain, Vol. n/a, pp. 65 - 68, September, 2012,
| Abstract | BibTex
R. M. Martins, N. Lourenço, J.G. Guilherme, N. Horta, AIDA: Automated Analog IC Design Flow from Circuit Level to Layout, International Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Seville, Spain, Vol. n/a, pp. 29 - 32, September, 2012,
| Abstract | BibTex
N. Lourenço, N. Horta, GENOM-POF: Multi-Objective Evolutionary Synthesis of Analog ICs with Corners Validation, Genetic and Evolutionary Computation Conf. - GECCO, Philadelphia, United States, Vol., pp. 1119 - 1126, July, 2012,
| Abstract | BibTex
R. M. Martins, N. Lourenço, N. Horta, LAYGEN II – Automatic Analog ICs Layout Generator based on a Template Approach, Genetic and Evolutionary Computation Conf. - GECCO, Philadelphia, United States, Vol. n/a, pp. 1127 - 1134, July, 2012,
| Abstract | BibTex
N. Lourenço, N. Horta, LAYGEN - Automatic Analog ICs Layout Generator, Conf. on Telecommunications - ConfTele, Peniche, Portugal, Vol. 0, pp. 165 - 168, May, 2007,
| Abstract | BibTex
N. Lourenço, M.V. Vianello, J.G. Guilherme, N. Horta, LAYGEN - Automatic Layout Generation of Analog ICs from Hierarchical Template Descriptions, IEEE PhD. Research in Microelectronics and Electronics - PRIME, Otranto, Italy, Vol. 0, pp. 213 - 216, June, 2006,
| Abstract | BibTex
N. Lourenço, N. Horta, LAYGEN – An Evolutionary approach to automatic analog IC Layout Generation, IEEE Conf. on Electronics, Circuits and System, Gammarth, Tunisia, Vol. 1, pp. 1 - 2, December, 2005,
| Abstract | BibTex

Projects

Closed Projects7

Acronym	Name	Funding Agency	Start date	Ending date
AIDA-C	AIDA-C: Analog IC Optimizer	Thales Alenia Space	01-10-2013	01-11-2021
DISRUPTIVE	DISRUPTIVE - A Paradigm Shift in the Design of Analog and Mixed-Signal Nanoelectronic Circuits and Systems	FCT	01-04-2013	01-12-2016
GENERALISE	Generative AI for Analog Chip Design	Sony Advanced Visual Sensing AG (Switzerland)	01-05-2023	01-04-2026
HAICAS	Hierarchical Analog IC Automatic Synthesis	IT	01-05-2020	30-04-2022
LAY(RF)^2	Ready-to-Fabricate RF and mmWave Integrated Circuit Layouts	IT	01-02-2020	31-01-2022
OPERA	OPERA - Layout-Aware Analog IC Design Automation	IT/LA	01-03-2014	01-02-2016
PROMISE	PROgrammable MIxed Signal Electronics	EU/H2020	01-01-2020	31-12-2024

Other Scientific Achievements

9Awards

N. Lourenço, R. M. Martins, A. Canelas, R. P. Póvoa, N. Horta, Best Paper Award 2019 - Integration, the VLSI Journal, N. Lourenço, R. Martins, A. Canelas, R. Póvoa, and N. Horta, “AIDA: Layout-aware Analog Circuit-Level Sizing with In-Loop Layout Generation”, Integration, the VLSI Journal, 2016. DOI: 10.1016/j.vlsi.2016.04.009, 01-07-2019
D. Guerra, N. Lourenço, A. Canelas, R. P. Póvoa, N. Horta, R. M. Martins, Best Paper Award Runner-Up - International Conference on SMACD, Daniel Guerra, António Canelas, Ricardo Póvoa, Nuno Horta, Nuno Lourenço and Ricardo Martins "Artificial Neural Networks as an Alternative for Automatic Analog IC Placement", International Conference on SMACD 2019, Switzerland., 01-07-2019
F. Passos, R. M. Martins, N. Lourenço, E. Roca, R. Castro-López, A. Canelas, R. P. Póvoa, N. Horta, F. V. Fernandez Fernandez, Best Paper Award, Best paper award in SMACD 2018, 01-07-2018
R. M. Martins, A. Canelas, N. Lourenço, N. Horta, Best Paper Award at International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), "On-the-fly exploration of placement templates for analog IC layout-aware sizing methodologies," , in International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), Lisboa, Portugal, June 2016., 01-06-2016
R. M. Martins, N. Lourenço, A. Canelas, R. P. Póvoa, N. Horta, 1st Ranked on “Design Automation Competition” at International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), "AIDA: Robust Layout-Aware Synthesis of Analog ICs including Sizing and Layout Generation" at International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), Istanbul, Turkey., 01-09-2015
R. M. Martins, N. Lourenço, N. Horta, Silver Leaf Best Paper Award at IEEE Conference on PhD Research in Microelectronics and Electronics (PRIME), “Analog IC Placement using Absolute Coordinates and a Hierarchical Combination of Pareto Optimal Fronts”, in IEEE Conference on PhD Research in Microelectronics and Electronics (PRIME), Glasgow, Scotland, June 2015., 01-07-2015
R. P. Póvoa, N. Lourenço, N. Horta, JG Goes, Nominee for Best Student Paper Award at IEEE International Symp. on Circuits and Systems (ISCAS), A Voltage-Combiners-Biased Amplifier with Enhanced Gain and Speed using Current Starving, Lisboa, Portugal., 01-05-2015
R. P. Póvoa, R. Lourenço Lourenço, N. Lourenço, A. Canelas, R. M. Martins, N. Horta, Best Student Paper Award Runner-Up at IEEE International Symp. on Circuits and Systems (ISCAS), LC-VCO Automatic Synthesis Using Multi-Objective Evolutionary Techniques, Melbourne, Australia., 01-06-2014
R. M. Martins, N. Lourenço, S. R. Rodrigues, J.G. Guilherme, N. Horta, Honourable Mention on “Design Automation Competition” at International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), “AIDA: Automated Analog IC Design Flow from Circuit Level to Layout”, in International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), Seville, Spain, Sep. 2012., 01-09-2012

1Prototypes

F. Passos, R. M. Martins, N. Lourenço, DDCC VCO (2.4GHz, 0.35um)

1Tutorials

N. Horta, N. Lourenço, Analog IC Design Automation: Approaches and Challenges

Other Contributions

6Conference Committees

International Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Conference co-chair, 2020
IEEE PhD. Research in Microelectronics and Electronics - PRIME, Conference co-chair, 2019
International Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Conference co-chair, 2019
International Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Conference co-chair, 2017
IEEE PhD. Research in Microelectronics and Electronics - PRIME, Conference co-chair, 2016
International Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Conference co-chair, 2016