@ARTICLE {19075,
author={N. Lourenço and R. M. Martins and A. Canelas and R. P. Póvoa  and N. Horta},
doi={10.1016/j.vlsi.2016.04.009},
journal={Integration, the VLSI Journal},
title={AIDA: Layout-aware analog circuit-level sizing with in-loop layout generation},
year={2016},
month={September},
volume={55},
number={09},
pages={316-329},
ISSN={0167-9260}
}